Globally Asynchronous in FPGA

Hello

Let me ask one question.

From my small experience, I find that FPGA is good for synchronous

design, because (1) There are enough registers, (2) There are fat clock trees for entire chip, (3) There are IPs for different clock synchronization management (for example, DCM).

Question is that

If we design very complex systems that contains many IPs that (1) different IPs need different clock domains, (2) different communication buses (for example, PLB, OPB) need different clocks, (3) single clock has too many loads,

Then how can current FPGA handle?

I think that following will be good in FPGA (1) Each IP has its own clock, (2) IPs communicate with "asynchronous handshaking" each other.

Reply to
Pasacco
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Dear P., Let me answer your question. IP should have a clock port and a clock enable port. So, if you need to integrate several bits of IP, you can use one clock with different enables. HTH., Syms.

Reply to
Symon

Thank you but I do not get the point.

Problem was that

--------------------------- If there is single global system clock, the overhead (by having only one global clock) becomes bigger and bigger.

---------------------------

My question was that

----------------------------- Can FPGA come up with "Globally Asynchronous, Locally Synchronous (GALS)" design style that ASIC tends to do? If yes, how?

-----------------------------

Thank you again

Reply to
Pasacco

This would require the possibility to have a lot of independend locally clock resources (like Actel quadrant clock). But how many would you suggest? Each independend clock resource is potentially slowing down the device when needing one global clock for the whole device. Second point is, that you can't locate a ff free over the whole chip, when you devide the chip in lets say 16 clock zones. You may end up in trouble when you need 50% of the chip with one clock, if the FPGA is designed to assume 16 equal sized parts. I think the fpga vendor has to do some trade-off in order to design parts that fit for most part of the market. As soon as the majority of the market needs 16 or 32 independend local clock you will have them on your desktop (give 12-18 month until an announced device will be really delivered :=)

bye Thomas

Reply to
Thomas Stanka

True if the logic domains are not interconnected. Otherwise maintaining synchronization also requires significant overhead and intellectual investment.

global buffers, handshakes, fifos, etc.

-- Mike Treseler

Reply to
Mike Treseler

By choosing to implement in an FPGA, you must accept the limitations of th architecture of the target device, including the number of permitte clocks. This may restrict the design style to some extent.

In an ASIC you (generally speaking) have no such restrictions, but th up-front cost and turn-around times are much increased.

clock

Reply to
RCIngham

All (afaik) FPGAs are capable of running a single global clock over the whole chip, so long as you use the resources provided for that purpose. The chip maker takes care of the distribution problems. If you want multiple clocks so you can shut down an area & save power, most modern FPGAs offer several clock nets. But you are now responsible for synchronising them.

Reply to
David R Brooks

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