Hello
Let me ask one question.
design, because (1) There are enough registers, (2) There are fat clock trees for entire chip, (3) There are IPs for different clock synchronization management (for example, DCM).
Question is that
If we design very complex systems that contains many IPs that (1) different IPs need different clock domains, (2) different communication buses (for example, PLB, OPB) need different clocks, (3) single clock has too many loads,
Then how can current FPGA handle?
I think that following will be good in FPGA (1) Each IP has its own clock, (2) IPs communicate with "asynchronous handshaking" each other.