Global clock as input of a FF

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when trying to sample a global clock as shown in the process,
the QuartusII 4.2 Design Assistant shows the critical warning
that clocks should only feed input clock ports.

So what can I do about that ? I need to sample the clock to find out
where the center of the clock period is.

I also get the critical warning that there are delay chains in my
synchronous design. The Design Assistant tool recommends not to use
any delay chains in synchronous designs.

I do not know how the delay chains did arise.
So how can I comply with the Design Assistant tool to remove the delay
chains ?

Thank you very much for your help.

   if rising_edge(Clk_fpga_fast) then
      l_sample1 <= '0';
      l_sample2 <= '0';
      l_sample3 <= '0';
      l_sample4 <= '0';
      l_sample5 <= '0';
      l_sample6 <= '0';

      if Enable_highspeed='0' then
         l_sample1 <= Clk_fs;
         l_sample2 <= l_sample1;
         l_sample3 <= l_sample2;
         l_sample4 <= l_sample3;
         l_sample5 <= l_sample4;
         l_sample6 <= l_sample5;
      end if;

   end if;
 end process;

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