In my design (in a Virtex II) there are 2 clocks, each of them on global buffer and feeding 2 sets of distinct registers (block A and block B). The clocks then feed a clock switching circuit (not a BUFGMUX) and the resulting clock feeds another part of the design (block C). From PAR report I get
WARNING:CLK Net:FPGA_CLK_BUFGP may have excessive skew because 1 NON-CLK pins failed to route using a CLK template.
WARNING:CLK Net:SMP_CK_MASTER_TO_CPU may have excessive skew because 1 NON-CLK pins failed to route using a CLK template.
I suppose this message warns about a potentially unacceptable skew between blocks A/B and block C , but the skew inside block A or block B is still guaranteed to be low.
Am I right ? Thanks