GLKP and GLKS

What is the difference between GLKP and the GLKS?

I am trying to figure out if i have enough global clock resources for the clocks. Right now I have about 7 clocks coming into the GLKP pins. When i instantiate a bufg, does it matter if its a bufg for GLKS or GLKP? Is there something to take into consideration between P or S or can i act like all of these are global buffers giving me 16 buffers in total?

Any help would be appreciatd thanks.

Reply to
Vivek
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clocks.

Were you planning to tell us what chip you are using?

Philip Freidin Fliptronics

Reply to
Philip Freidin

I am using the virtex II. Sorry about that.

Reply to
Vivek

In a Virtex-II part.

There are several constraints on which global buffers and clock nets and clock pins can be used in a single design. The shared resources make certain selections mutually exclusive.

Here are some examples:

Although there are 16 global clock buffers (and therefore

16 global clock nets), you can only use 8 global clocks in any quadrant of the FPGA. If your design uses 8 or less clocks, then this is not too big a deal. When you use 9 through 16 clocks, you have to floor plan your design so that all the logic in any quadrant does not use more than 8 clocks. (There may also be constraints on which of the clocks these 8 can come from)

Adjacent global buffers share their inputs. If they are using separate clocks, this is not too much of a problem, but if you are using the BUFGMUX function, then this uses both signals, which makes the adjacent BUFGMUX either useless, or it must use the same inputs.

Primary and secondary buffers on opposite sides of the FPGA share some output resources. This means that if they are mutually exclusive to a quadrant. Confused yet? (If BUFG1P is used to drive logic in the NW quadrant, then BUFG1S on the opposite side of the chip can not drive into the NW quadrant)

Then add in constraints of access to DCMs, and which DCM outputs go to which buffers, Differential clock inputs, and probably more stuff, and you have a pretty fun puzzle.

At a minimum, you need to read this document:

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pages 58 through 77.

In prior FPGA generations, The primaries had faster connections to the clock input pins, but less clock source options. The secondaries had more signal source options, but were a little slower. In V-II, since they share inputs, it would seem that the only difference is the name.

So you aren't yet at the 8 clock max per quadrant limit.

Yes. As the example above (here it is again) (If BUFG1P is used to drive logic in the NW quadrant, then BUFG1S on the opposite side of the chip can not drive into the NW quadrant)

This is regardless of how many clock nets you have.

There are 16 buffers, and there are 16 global nets on their outputs, and there are 8 clock nets in each quadrant. To have

16 global clocks in a design takes some extremely careful planning, and floor planning of logic at least into quadrants.

You really need to read the above reference, and then you can refine your learning with the FPGA editor, where you can (with considerable effort) see these interactions.

I would describe this all as gratuitiously complicated, but what do I know?

Philip

=================== Philip Freidin snipped-for-privacy@fpga-faq.com Host for

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Reply to
Philip Freidin

Howdy Vivek,

You mentioned in another email that you are using a Virtex-II. Assuming you only need the 8 clocks or less in that device, I would suggest using either only GLKP's or only GLKS's (it doesn't matter which - they are functionally identical). By using only one or the other type, you avoid any issues with getting all 8 clocks into any and all quadrants of the device.

The following link points to where more detailed info can be had on the GLK limitations:

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See the "facing GBUF" rule, shown in figure 3-7 of the user guide.

Have fun,

Marc

Reply to
Marc Randolph

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