Hi All, I have a state machine which produces control signals (synchronous Reset and Enable) for a synchronous counter. The control signals are generated based on the current state and a 8 bit data input. I am seeing glichtes in both output control signals near the rising clock edges. The 8 bit data input is registered. Is there any way to get rid of the glicthes?
The VHDL code looks something like this
FSM: process(CurrentState,DataIn,Count,NewFrame,...) begin CntrRst