Getting Started With Simple Sound Synthesis

The VGA interfaces I've seen all have something of the form

--pin1 -- R --| |

--pin2 -- 2R --+---monitor |

--pin3 -- 4R --|

so maybe something like that would produce a really, really cheap DAC for the output stage.

I'd be tempted to build various circuits of the form

• At each tick, add INPUT_1 to my internal 24-bit register

• If my internal register reaches INPUT_2, set it back to zero

• Put the value of (maybe the top 8 bits of) my internal register on OUTPUT

If the value of INPUT_1 is more than INPUT_2, output 0, otherwise output 1

If the value of INPUT_1 is more than INPUT_2, output INPUT_3, otherwise output INPUT_4

(do you want a single-bit or a wide version of this? I don't know yet)

and then try to build some sort of switching fabric for connecting various constants and the outputs of circuits to the inputs of others in a programmable way - a sort of field-programmable audio-generation array inside an FPGA.

I think that's flexible enough to do what I remember the sound chip on the BBC Micro being capable of: you can use a ramp and a network of switches to provide an envelope, a ramp and a VAG produce a square wave of arbitrary aspect ratio, a slow ramp driving INPUT_1 of another ramp produces a wave of constantly rising frequency.

Have fun!

Tom

There's an article floating around somewhere on the Net describing the implementation details of the SID (an interview with the original designer).

Basically, it's very simple. First, you need a NCO (Numerically Controlled Oscillator) to produce a waveform. A NCO is nothing but a simple counter that's incremented with a constant at a fixed rate. By changing this constant you can change the frequency of the waveform. Usually the counter is 24 bits, and the waveform is created from the top 8 bits, which can be used as an index to a sample-table (a crude form of resampling). In the SID, for a square wave, the top bit is used as output; for a saw wave, the top 8 bits; for a triangle wave 7 of the 8 topbits are used, and these are followed by a XOR gates to invert the bits when the top bit is set. After these, a simple R2R ladder that acts as DAC which is followed by an amplifier and a filter.

This same NCO approach can also be used for the envelopes, but I think in the SID, this was all analogue stuff using resistor, capacitors and comparators. I believe the amplifiers were simple CMOS switched resistor ladders, as were the filters.

I think you could all the digital stuff in a smallish FPGA; coupled with some analogue components it would make a well reverse-engineered SID. Forget all noise defying PCB practises for the final touch. Attempting to it do it completely digitally means you have to design-in its flaws too.

But you don't want to do a complete SID; all you need is a simple NCO, which is only a few lines of VHDL. What will it interface to?

Jeroen

Controlled

counter

counter

can be

the SID,

top 8

After

...

NCO, which

Thank you, Jeroen, that was very helpful. The synthesizer will interface to a homebrew CPU in my FPGA.

Do I recall SID had a noise source as well? Would a LFSR be suitable? Thanks.

-Dave

Actually, the SID used a LFSR for that :))

Xilinx has an app note for a sigma-delta converter design that just requires an external R and C. Also companies like AKM and Crystal have CD quality converters that are just a couple bucks and pretty easy to use.

Jeff