Getting Gate Counts from Quartus

In the report window, click the 'Fitter' item, then select the "Resource usage" item.

Best regards,

Ben

Ben,

I tried that and I didn't find anything specific for gates, just LUTs and logic elements. Am I missing something?

Adam

Ben Twijnstra wrote:

Hi Adam,

Er... yes, namely the marketing-gate count. The smallest design unit either in a Xilinx or an Altera FPGA is the LUT.

Until around 2002 both Altera and Xilinx used a marketing-department-driven equivalent ASIC gate count. Since the metrics used by Altera and Xilinx for these gate counts were not the same, there was a horrendous amount of confusion, bickering, name-calling, etc, etc. Thus, here on comp.arch.fpga this gate count equivalent was quickly dubbed 'marketing gates'.

With the introduction of the Cyclone and Stratix FPGA's, Altera dropped the 'equivalent ASIC gates' formula, since every ASIC engineer laughed his/her head off when presented with these figures. I don't know why Xilinx still sticks with the number - but whatever figure you see in ISE, it's WRONG.

So, I suggest that you simply ignore that equivalent gate count stuff. If you need to retarget your design to an ASIC, get a copy of Synplicity's or Mentor's tools, pick the library you need, and see what comes out.

Best regards,

Ben

Hey, Mabe this helps. this is primarily for APEX devices but it will give you some idea