Hi folks
I'm working with Synplify Pro (8.5.1) and I'm trying to test whether VHDL code is synthesizable. How can I do this without selecting a specific vendor or chip? Is it possible? I thought there might be some concept of a generic target, but can't find anything of the sort.
In particular, I want to get the mapped VHDL file from Synplify and bring it back into ModelSim for simulation and functional verification. So, to tell whether my code is synthesizable, I have to do the following:
- Select a specific chip
- Run the synthesis
- Bring the mapped VHDL netlist file into ModelSim
- Bring vendor specific files into ModelSim because they are required by mapped file.
- simulate for that chip.
Is there another way?
Thanks in advance, Richard