Hi, I've written the code for an application using Xilinx 7.1 . Can I create an IP core out of it?
Thanks and Regards, Srikanth
Hi, I've written the code for an application using Xilinx 7.1 . Can I create an IP core out of it?
Thanks and Regards, Srikanth
Hi, I've written the code for an application using Xilinx 7.1 . Is it possible to I create an IP core out of it?
Thanks and Regards, Srikanth
well what you have done already is an IP core, so what is what you actually want todo?
a
Take for example, FIFO or that sort of IP core from coregen. I want to generate a similar stuff which packs instanciation template and synthesize output file.
Thanks and Regards, Srikanth
there is (almost) no standard for IP core generators (SPIRIT is only used by Actel so far)
in ISE 5.1 it was possible to add custom IP cores to coregen but in later version this functionality is no longer available :(
Antti
I might owe you some royalties. In the future I will use
a
How do you create a targetted netlist version?
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