Hello, Please answer my following questions.
Q1. At Xilinx site I've read that Coregen is not available with ISE Webpack. But I've got a requested trial CD of ISE WebPack contains the Coregen. So please tell me about this conflict. Is the coregen available with ISE foundation contain additional features and functionalities and that of webpack limited one?
Q.2.I am generating 32x1 Asynchronous FIFO in Block Memory of Sparatn-II in CoreGen of my ISE web pack5 (trial version). But in the data Port Parameters I am unable to give the FIFO depth of
- Rather the minimum depth available for this FIFO is 15 irrespective of FIFO width. Please tell me how can I generate a 32X1 Asynchronous FIFO in coregen5? Can I do this directly? If, no, then can I do this by generating 32x15 FIFO and only use the first depth (depth1) and not use the depth 2-15?
Thanks and Regards Atif