General Number Field Sieve in FPGA

'General Number Field Sieve' is more a system than a task, simply breaking down the task of factoring a big number into implementable chunks is quite a job. The place to look is probably the SHARCS conference reports (Special- purpose Hardware for Attacking Cryptographic Systems):

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has links to the slides for the 2005 and 2006 conferences, the VAMPIRE project of ECRYPT is source of much of the funding.

As far as I know, the status is:

people have implemented ECM on large FPGAs, it's faster than a P4 but not faster-per-dollar

the designs people have proposed for lattice-sieving and linear algebra are all special-structure hardware with a structure very different from FPGAs, particularly in terms of memory per logic-element; it's not clear they could be helpfully fitted into FPGA. In any case they tend to propose rather peculiar external memory configurations (huge fast memories plus large extremely-fast memories) so you'd have to build costly custom boards before being able to test anything.

to do anything very interesting is likely to require hardware costs and engineering effort well beyond the casual.

Tom