Gated clock question

They're almost impossible to implement without getting glitches. Use clock enables instead. If your prototyping an ASIC, and can afford it, SynplifyPro will do automatic clock gate to enable conversion.

Cheers, Jon

Short version:

Putting a clock through logic leads to skew, jitter, runt pulses, and lots of other horrible things. These all make life far harder for the implementation tools, which work on the assumption that you're not a moron. FPGA logic fabric was designed for synchronous logic design. If you need to switch a clock on and off "globally" (e.g. for power saving), some devices have dedicated "clock multiplexor" resources to do this.

Gate your clocks, and your designs will run slower. Your tools will run slower. Your designs will stop working inexplicably when they warm up or cool down. Your logic will cease to work when you buy a new batch of chips. Your wife will leave you for a younger man and your pot plant will die. Just don't do it!

-Ben-

P.S. You *really* don't want to hear the long version.

In addition to all the other comments already made there is the basic problem that every time you re-run the build process the timing of the generated clock, relative to it's source, will be different. The result can be a nightmare of the design sometimes working, or not, and if you are very unlucky a half way house between working and not.

That said if you are gating (dividing) by using a flip-flop then you can do something in this area. Your generated clock will still differ in timing relationship to the source clock. Factors such as build, silicon batch, voltage, temperature will have a variance on this timing.

The only time I would use this is if I had a large design, that had a variable enable function (non regular 1 in N clocks), was also resource critical (tight squeeze in chip), to sit on the (gated) clock. By not using local clock enables you can save some resource.Otherwise I would use a clock enable or something like a DCM to divide, or control, the clock. If you do use a flip-flop control then extreme care will need to be taken in passing signals, or data, between the generated clock domain and source clock domain. All the usual non-related clock domain signal interfacing techniques will need to be used.

John Adair Enterpoint Ltd. - Home of MINI-CAN. FPGA CAN Bus Development Board.

Thanks to all of you, guys, you have been really very helpful! Actually, I suspected there might be glitches when gating a clock, now things are quite more clear.

schrieb im Newsbeitrag news: snipped-for-privacy@z14g2000cwz.googlegroups.com...

If done propperly, also clock gating is safe. But is has to be done PROPERLY!. As otheres already noted, FPGAs are not directly designed to support clock gating. Use clock enable and you will sleep well ;-)

Regards Falk

More over sometime gated clock is the only way as clock enable will not stop the power consumption. If not all than most of the cellular phone in the market and similar product which you want to work for long time but have limited power supply work with gated clock. So you CAN have RELIABLE gated clock design. Saying so obviously this should not be the normal route but the exception one. Have fun.

Hi Berty,

Of course you can have reliable gated clock designs...but FPGAs are not conducive to them. I believe most all if not all the chips used in cell phones are custom chips and not FPGAs. Do you know of any current production level cell phones with FPGAs in them?

Regards,

Austin

I use a Spartan 3 and the ISE software. Now that I'm bringing all the different parts of my project together, I have this problem with the gated clock. I don´t have a clue how to solve it out. It appears in the "Generate Programming File" part: WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net a1_1 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. I tried introducing the clock in a flip-flop whith a CE pin and controllin it, but it was no use. So I don´t use it anymore. It's really weird, cause I add a memory, it's mapped properly, and this dammed warning pops out. With this warning the core doesn´t work propperly in the FPGA. My design clock is 5MHz, so I guess I can´t use the DCM (in case it helped). What can I do? Would it help if I changed the synthesizer and use, say, Simplicity's Simplify software? I would be extremely thankful if anyone could help me. I MEAN IT. Thanks

different parts of my

clue how to solve it

by a combinatorial pin.

dammed warning pops out

Hmm. It looks like you've (literally) got some wires crossed. I suggest:

• Find all references to this net called a1_1 in your design. * Identify what exactly generates it. * Identify where it's used. * Identify what clock pins it's connected to. * ... * profit!

Judging by the name, a1_1 is probably part of a bus of some sort. Most likely you've just made a typo when connecting up some ports. If so, it should be easily fixable. If not, and there really is some logic in one of your clock paths, well you'll need to spend some time analysing what the circuit's supposed to do, and figure out how to do that *without* gating the clock.

Good luck,

-Ben-

You may want to bring your gated clock to an IO pin and back into a GCLK pin.

dbrown

"David Brown" schrieb im Newsbeitrag news: snipped-for-privacy@adelphia.com...

I dont think so. Fix the design. Do what the tool is telling you. DONT use a gated clock, use a clock enable instead.. Search your (VHDL?) code after

if clk'event

or

if rising_ege(clk)

stuff. Only real clocks (tm) should appear there. If there is any signal generated like

my_damm_gated_clock

I think it will depend on how the gated clock is used and how much logic it clocks.

I have done hundreds of designs with gated clocks and multiple clock domains in FPGAs and ASICs and there's nothing wrong with it as long as it's a good gated clock design. The main issue with gated clocks in FPGAs is they don't usually go to internal global buffers and there can be clock skew in the clock tree. If a good gated clock aproach is used, and it is fed out of the device and back in to a global clock pin the design will work fine and will reduce the power.

To side with Falk, if the design is only a few flip flops, there is nothing unusual about the clock divide by frequency, and power is not an issue, then you can go back and add clock enables to your code and achieve the same result.

David Brown

Let's not forget that Virtex-2 and later FPGAs have, hidden in the Global Clock buffer, not only an Enable input, but also a clock multiplexer. That multiplexer in Virtex-2 must use a synchronous select to avoid glitches, but the BUFGMUX_VIRTEX4 is implemented in such a clever way that the S input can be changed at any time, never causing a glitch. There is a detailed description in the Virtex-4 data sheet, under Global Clocking Resources, page 85 of the August 2004 printed data book.

Peter Alfke, Xilinx Applications