Funky experiment on a Spartan II FPGA

For a worst-case look, I would implementa maximum-lemgth shift register and toggle its front end. Driven by a global clock,this generates the maximum amplitude of synchronous spikes on the Vcc distribution. Anything more realistic would spread out the spikes, thus lowering the amplitude. I suppose you know how to access the internal Vcc and Vdd levels, and bring them to the outside. My question is: What do you want to prove or disprove? Peter Alfke, from home.

this bit has me lost, how can you use a picoblaze in the reset state ?

yes, it is widely known, and is a more typical usage of PFGA,

You could also implement a 'sea of 32 bit CE counters', which can be usefull to calibrate and verify your system - that is a pattern that should not overheat the FPGA, but will give a stable spectrum. Enable/disable of the ClockEnable, would also give results for the clock tree and (plus) the logic fabric.

-jg

Peter,

Thanks for your suggestion. This is essentially a curiosity driven experiment. We saw a paper in the Intel Technology journal , where they had such impledence measurements for the P4 processor. We were wondering if we could reproduce those measurements in our lab, and decided to start with FPGAs rather than processors as a first baby step. The paper is located at:

Also, just checking if I understand you right : are you suggesting that I implement one huge shift register, and then just push a 10101... pattern through it ? it seems like a good idea.

Jim,

Since I donot really want to do any real computations using the Picoblaze, i think its okay to hold it in the reset state. I just want to clock it at different frequencies and see what happens on the power delivery network

Thanks for your suggestion about the clock enable. It makes a lot of sense.

Regards, mammo

Correction, before anybody points out my error: The long checkerboard shift register is a popular way to measure power consumption, but it is actually very benign with respect to Vcc spikes, since half the loads go Low and half go High, nicely compensting each other. The tougher test is to switch every bit in synchronism, from Low to High on one clock, and from High to Low on the next, etc. Needs a line to drive all D inputs together, and this line being toggled. This is of course not a realistic test, and it may show real ugly results. But I think that's what you were after... Sorry for the misleading previous posting. Peter Alfke, Xilinx (from home)

There are two portions of clock consumption, one is the clock network itself, and the other is the Nodes/Fabric that toggle. Not all data makes that distinction.

So Peter's more agressive test of a 101010 shift register will have two power levels, depending on the ClockEnable. Wide counters have a more typical logic % usage.

If you Pinmap, and add an OE term, you can also get the IO fabric power values.

The separate supplies on FPGA makes probe of the internal power rails more difficult.

-jg

Hi Mammo,

I think this would be a great project, and a useful paper to present for others too.

I'm not sure why Peter is talking about worst case, as Xilinx has already said the larger parts lack margin to operate at the highest frequencies with worst case design loads due to power and thermal issues. Besides the lack of cooling for worst case loads, most boards also lack the power supply margins too ... and will go unstable at worst case loading at high clock rates due to dynamic power.

It would be nice (and I've asked for this before with very negative responses) that Xilinx openly document the dynamic power and thermal limits. As a side note, this problem is partially mitigated by clock skew as the parts get larger, but that doesn't help realize designing for worst case loading, or even having a clue to predict why one placement works and another fails, when the skew stacks up worst case in your design.

Have fun!! ... and I look forward to your results :)

John

mammo wrote:

To implement both would be a good idea. That way, you have two tests with similar node-toggle rates, but different Icc profiles. Another would be to configure (tiled) half the device as PosEdge and half as NegEdge, as that shifts the fabric currents. (but not the Clock-tree currents ).

-jg

Hey people,

Thanks for all the suggestions... will keep you guys posted.

Best, mammo

Can't this be documented by measureing dynamic current and voltage delivered to fpga. And a ambient and fpga case temperature probe..? The rest should be math and bitpatterns.

Hi Peter,

could you please further elaborate this ?

How is the checkerboard shift register different than the switching of every bit from high to low in terms of Icc and Vcc ?

I would think that Icc behaviour is the same in both cases but what about Vcc ?

If Vcc behaves different in both cases, what is the reason ?

Thank you.

Xilinx gives complete data on thermal resistance with and without heatsink and airflow. We cannot give blanket data for power consumption, because it depends on the aggregate frequency times capacitance product of every node (assuming the same Vcc for all of them). That is a problem shared by all programmable devices, but not shared by ASICs and ASSPs, like microprocessors. They usually operate under fairly well-specified internal conditions. FPGAs do not.

"Worst case" would be a shift register running at max frequency. Such a design is not only unrealistic, but would most likely overheat even with the best heatsink. But if you reduce the frequency, you can easily test this "worst-case" design. Just do not overdo the frequency... Peter Alfke

Maybe one could hint it with power vs frequency diagrams under worstcase condition. And mathematical models of behaviour. And transient powerconsumption during worstcase scenarios.

Xilinx offers power-estimation software that is getting better with each generation. I see no benefit in documenting perverse extreme situations that no realistic design would ever encounter. Peter Alfke

Peter Alfke schrieb:

Hi Peter,

could you please further elaborate this ?

How is the checkerboard shift register different than the switching of every bit from high to low in terms of Icc and Vcc ?

I would think that Icc behaviour is the same in both cases but what about Vcc ?

If Vcc behaves different in both cases, what is the reason ?

Thank you.

lenz,

You really have to draw yourself a picture.

I don't think anyone has really thought this through, unless they are doing it in reality.

For example, if I place a 1,1,1,1,... in a shift register, and clock it, I get a transition from a 1 to a 1, and no charging or discharging, so no current!

If I place 1,0,1,0,1,0 ... in the shift register, then I maximize my average dynamic current, as on every clock, I make a node change from 0 to 1, or 1 to 0.

If I place an isolated 0 to 1 transition I can see the effective impulse response for a single transition of 0 to 1. This would have to be done with all the DFF tied to the same D input, and not a giant shift register, however.

One has to examine how the skew across the global clock will affect the outcome (nothing is really synchronous in reality - never all the exact same phase).

So, there are many experiments one can perform, and as Peter points out, many of them are degenerate cases (unlikely to exist in reality).

These are exacly the kinds of patterns we use in verification and charaterization. And, we have been doing this for many years now.

Austin

The assumption may have been made (but not thoroughly communicated) that shifting would be through SRLs to deliver the max power. Transition of every *register* from 1s to 0s would be one heck of a strain but perhaps not as much of a strain as half that many SRLs (SLICEM vs SLICEL these days) feeding an all-1 to all-0 transition on the registers fed by those SRLs.

John_H,

I don't doubt that one can construct a ultra worst case scenario. We have done that in the past.

Part configures, DONE goes high, and then after a few clocks, the part configures, DONE goes high....

You get the picture. The thump from the switching resets the entire power on reset circuit, and the part starts all over again.

A very very expensive relaxation oscillator, whose output is the DONE pin.

What is far more important is for the customer to know how much system jitter there will be for their pcb, their bypass network, and their bitstream. THAT is a real problem!

Aust> The assumption may have been made (but not thoroughly communicated) that

When you shift a 1010101 pattern, there is a lot of power consumption, but on each transition half the nodes go Low-to-High, and the adjacent other half goes High-to-Low. I call that benign. If you switch on every even clock cycle from 1111111 to 0000000 and on every odd clock cycle back to 11111111, you do not get the compensation effect, although the total average power consumption is the same. I hope this is clearer. Peter Alfke