Hi out there,
maybe someone can give her/his opinion:
I have the following assignment in my top level file:
entiy top is port ( ... Sdram_csn : out std_logic_vector(1 downto 0); ... ); end top;
architecture rtl of top is
... begin
Sdram_csn
Look at creating a .do macro with Modelsim that adds the signal with the add wave command. Look at the syntax that the input and output signals are declared with in the signals window when you've simulated and follow that format.
The very first thing you should do when you get a function gate mismatch is to go back to your static timing analysis report and verify that there are no timing violations reported.
The second thing is to verify that your testbench meets the setup & hold requirements for the "real" part. This applies both to outputs from the tb and inputs to it.
The third thing is to make sure that any combinational processes in your RTL have *all* of the input signals in the sensitivity list.
This will take care of 99.9% of mismatches. Any remaining issues will be the proverbial 5% that takes 95% of the time. :(
-- Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
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