is it true that one-hot encoding for FSM's is used in FPGA's? If so, why? is it due to the large amount of registers available i.e: enough registers to store all states? what kind of encoding is using in ASIC's?
thanks much
-- avi
"is it true that one-hot encoding for FSM's is used in FPGA's? If so, why? is it due to the large amount of registers available i.e: enough registers to store all states? "
Yep!
have a look at this:
Florian
--
int m,u,e=0;float l,_,I;main(){for(;1840-e;putchar((++e>907&&942>e?61-m:u)
["\t#*fg-pa.vwCh`lwp-e+#h`lwP##mbjqloE"]^3))for(u=_=l=0;79-(m=e%80)&&
I*l+_*_
It sure simplifies decoding states.
I think the real answer is that overall, it fits well with the available hardware resources. At least for some/many problems.
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With a good synthesizer, you can specify any encoding you want. One hots can run at higher frequencies and usually result in less combinatorial logic.
Try it both ways and see for yourself. Be sure to cover all the state cases.
see thread:
-- Mike Treseler
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