Hi,
You're right. I never connected to outside world with the FSL bus defined internally. I connect MicroBlaze signals directly to outside. I will inform the team about this.
In this case, I would solve this by creating a dummy peripheral which just tunnels the FSL signals through to the outside world.
The .mpd file would look like something like this:
BEGIN FSL_TUNNEL_TO_OUTSIDE OPTION IPTYPE=PERIPHERAL OPTION IMP_NETLIST=TRUE
# Define bus interface BUS_INTERFACE BUS=MFSL, BUS_STD=FSL, BUS_TYPE=UNDEF BUS_INTERFACE BUS=SFSL, BUS_STD=FSL, BUS_TYPE=UNDEF
# FSL slave port PORT FSL_S_CLK = FSL_S_Clk, DIR=in, BUS=SFSL PORT FSL_S_READ = FSL_S_Read, DIR=in, BUS=SFSL PORT FSL_S_DATA = FSL_S_Data, DIR=out, VEC=[0:31], BUS=SFSL PORT FSL_S_CONTROL = FSL_S_Control, DIR=out, BUS=SFSL PORT FSL_S_EXISTS = FSL_S_Exists, DIR=out, BUS=SFSL
# FSL master port PORT FSL_M_CLK = FSL_M_Clk, DIR = out, BUS = MFSL PORT FSL_M_WRITE = FSL_M_Write, DIR = out, BUS = MFSL PORT FSL_M_DATA = FSL_M_Data, DIR = out, VEC = [0:31], BUS = MFSL PORT FSL_M_CONTROL = FSL_M_Control, DIR = out, BUS = MFSL PORT FSL_M_FULL = FSL_M_Full, DIR = in, BUS = MFSL
# FSL master signals coming in from outside PORT EXT_FSL_M_CLK = "", DIR=in PORT EXT_FSL_M_WRITE = "", DIR=in PORT EXT_FSL_M_DATA = "", DIR=out PORT EXT_FSL_M_CONTROL = "", DIR=out PORT EXT_FSL_M_FULL = "", DIR=out
# FSL slave signals going out to the outside PORT EXT_FSL_S_CLK = "", DIR=out PORT EXT_FSL_S_READ = "", DIR=out PORT EXT_FSL_S_DATA = "", DIR=in PORT EXT_FSL_S_CONTROL = "", DIR=in PORT EXT_FSL_S_EXISTS = "", DIR=in
END
The VHDL code will look like this:
library ieee; use ieee.std_logic_1164.all;
entity fsl_tunnel_to_outside is port ( -- FSL master signals FSL_M_Clk : out std_logic; FSL_M_Data : out std_logic_vector(0 to 31); FSL_M_Control : out std_logic; FSL_M_Write : out std_logic; FSL_M_Full : in std_logic;
-- FSL slave signals FSL_S_Clk : in std_logic; FSL_S_Data : in std_logic_vector(0 to 31); FSL_S_Control : in std_logic; FSL_S_Read : in std_logic; FSL_S_Exists : out std_logic;
-- FSL master signals coming in from outside EXT_FSL_M_CLK : in std_logic; EXT_FSL_M_WRITE : in std_logic; EXT_FSL_M_DATA : in std_logic_vector(0 to 31); EXT_FSL_M_CONTROL : in std_logic; EXT_FSL_M_FULL : out std_logic;
-- FSL slave signals going out to the outside EXT_FSL_S_CLK : out std_logic; EXT_FSL_S_READ : out std_logic; EXT_FSL_S_DATA : out std_logic_vector(0 to 31); EXT_FSL_S_CONTROL : out std_logic; EXT_FSL_S_EXISTS : in std_logic ); end entity fsl_tunnel_to_outside;
architecture IMP of fsl_tunnel_to_outside is
begin -- architecture IMP
FSL_M_Clk