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FSL State machine to read data in

Hello again

I hope this is the last time I have to contact the newsgroup concerning the FSL interface of the Microblaze processor. I just added a simple Adder modul, which sums up two input signals.

But there is one problem. The first and the second value are always the same, so the result is 2 times op1. So although I send 2 different values to my FIFO it only reads out the first one and this two times. Example: 2+3 =

4, 125+3= 250

Here is the corresponding code, i have divided the Adder in a Controller and Datapath Modul: Controller: Read is in this case the FSL_S_READ signal, Statemachine starts in the the IDLE State. Start is the FSL_S_Exists signal from the FSL interface. And Finish is the FSL0_M_Write! I have added a Wait Statement where the Read signal is Low for one clock signal, I tried to adopt it from the FSL Documenation!

comb: process(current_state, start) begin finish

Reply to
Roger Planger
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Hi,

First have you simulated this to see that the waveform is correct? Secondly you don't check for an Exists signal before loading breg.

We can take this offline if you want.

Göran

Roger Planger wrote:

Reply to
Göran Bilski

Oh you are great Goeran, I have just checked now for the exists signal a second time and it seems like that my adder works!!

Awesome! Now I will add my IP to be sure, that not the processor is executing the addition :)

Thanks so much!

Cheers R

Reply to
Roger Planger

Great that it works.

I have been doing some FSL modules and if you need more help optimizing your functions, just send me an email.

Göran Bilski

Roger Planger wrote:

Reply to
Göran Bilski

Okay thats tremendous, I think a little bit later on I will come back to this offer, when I extend the function of my IP

Thanks a lot

Roger

Reply to
Roger Planger

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