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frequency multiplication

Hi, for a re-desing i'd like to omit a 'standard' pll with counters etc. used for frequency multiplication, by a cpld. Among other things, the cpld has to perform a 128x frequency multipliction 48KHz to 6144Khz). Some (many) cpld's have on-board pll's but these are not usefull because they are inteded for clock distribution and the lowest operating frequency is much lower than

48KHz.

Therefor i'd like to implement a 'dpll' in a cpld, that can multiply 48KHz to 6144KHz, or is there perhaps another way?

Are there any free vhdl sources for this pll?

Best, Jim

Reply to
Jim
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Most DLL use a chain of buffers to stretch over a whole period. That limits the lower frequency end to something like 20 MHz (which might need a thousand stages of 50 ps each). In a CPLD, this is out of the question. Your best bet is an external PLL, or "knit your own" using an external VCO and do the 7-bit counting and the phase detector inside the CPLD.

Here is a weird idea: If your 6 MHz need not be a continuously running signal, but only the right number of pulses averaged over time, you could build an RC oscillator of, say, 10 MHz and turn it off after 128 pulses, on again at the beginning of the next 48 kHz signal. That could be done with 8 macrocells, 3 pins, and 2 resistors and one capacitor.... Just thinking out-of-the-box... Peter Alfke

Reply to
Peter Alfke

right

2

I am guessing from the numbers given by the original poster that this is for digital audio, probably an external clock being multiplied to drive an oversampling ADC clock input or something of this sort. If this is the case not only it has to be continuous, but it has to be low jitter too.

/Mikhail

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Reply to
MM

Even if it is for audio, the 6 MHz might be just for data storage, and so be independent of the audio rate. Peter Alfke

Reply to
Peter Alfke

if it is for digital audio: Use an external 6.144MHz VCXO and a portion of a CPLD for the clock divider and the XOR between clock divider output and your 48kHz word clock input. This solution has low jitter and give you a stable 6.144MHz. Useable for audio-DACs, AES3-encoders, etc...

And, dont forget a simple low pass filter (10k, 47n) between the CPLD output pin and the voltage-control-XO input.

WD

Reply to
Walter Dvorak

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