Frequency limitations?

Hi Everyone,

I tried to run the processor as well as the OCM with 100/100, 300/100,

300/300 as well as 300/150 MHz combinations. But the last ones are not working at all.

For the 300/300 as well as the 300/150 designs, I have also given C_DSCNTLVALUE as well as C_ISCNTLVALUE the values 0x81 and 0x83 respectively. But I am not getting any outputs. The algorithm is infact floating point intensive and the only thing I am trying to do other than these calculations is that I am trying to display some intermediate results through the OPB UartLite. Do you have any suggestions. I am attaching the mhs file of the 300/150 design below.

Joe

# ############################################################################ ## # Created by Base System Builder Wizard for Xilinx EDK 6.3 Build EDK_Gmm.10 # Wed May 11 10:28:47 2005 # Target Board: Memec Design Virtex-II Pro P7-ff672 Development Board Rev 3 # Family: virtex2p # Device: XC2VP7 # Package: FF672 # Speed Grade: -6 # Processor: PPC 405 # Processor clock frequency: 300.000000 MHz # Bus clock frequency: 100.000000 MHz # Debug interface: FPGA JTAG # On Chip Memory : 40 KB # ############################################################################ ##

PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = INPUT PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = OUTPUT PORT fpga_0_RS232_req_to_send_pin = net_gnd, DIR = OUTPUT PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = CLK PORT sys_rst_pin = sys_rst_s, DIR = INPUT

BEGIN ppc405 PARAMETER INSTANCE = ppc405_0 PARAMETER HW_VER = 2.00.c BUS_INTERFACE JTAGPPC = jtagppc_0_0 BUS_INTERFACE ISOCM = iocm BUS_INTERFACE DSOCM = docm BUS_INTERFACE IPLB = plb BUS_INTERFACE DPLB = plb PORT PLBCLK = sys_clk_s PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ PORT RSTC405RESETCHIP = RSTC405RESETCHIP PORT RSTC405RESETCORE = RSTC405RESETCORE PORT RSTC405RESETSYS = RSTC405RESETSYS PORT BRAMISOCMCLK = ocm_clk_s PORT BRAMDSOCMCLK = ocm_clk_s PORT CPMC405CLOCK = proc_clk_s END

BEGIN jtagppc_cntlr PARAMETER INSTANCE = jtagppc_0 PARAMETER HW_VER = 2.00.a BUS_INTERFACE JTAGPPC0 = jtagppc_0_0 END

BEGIN proc_sys_reset PARAMETER INSTANCE = reset_block PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT Ext_Reset_In = sys_rst_s PORT Slowest_sync_clk = sys_clk_s PORT Chip_Reset_Req = C405RSTCHIPRESETREQ PORT Core_Reset_Req = C405RSTCORERESETREQ PORT System_Reset_Req = C405RSTSYSRESETREQ PORT Rstc405resetchip = RSTC405RESETCHIP PORT Rstc405resetcore = RSTC405RESETCORE PORT Rstc405resetsys = RSTC405RESETSYS PORT Bus_Struct_Reset = sys_bus_reset PORT Dcm_locked = dcm_0_lock END

BEGIN isocm_v10 PARAMETER INSTANCE = iocm PARAMETER HW_VER = 2.00.a PARAMETER C_ISCNTLVALUE = 0x83 PORT ISOCM_Clk = ocm_clk_s PORT sys_rst = sys_bus_reset END

BEGIN isbram_if_cntlr PARAMETER INSTANCE = iocm_cntlr PARAMETER HW_VER = 3.00.a PARAMETER C_BASEADDR = 0xffff8000 PARAMETER C_HIGHADDR = 0xffffffff BUS_INTERFACE ISOCM = iocm BUS_INTERFACE DCR_WRITE_PORT = isocm_porta BUS_INTERFACE INSTRN_READ_PORT = isocm_portb END

BEGIN bram_block PARAMETER INSTANCE = isocm_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = isocm_porta BUS_INTERFACE PORTB = isocm_portb END

BEGIN dsocm_v10 PARAMETER INSTANCE = docm PARAMETER HW_VER = 2.00.a PARAMETER C_DSCNTLVALUE = 0x83 PORT DSOCM_Clk = ocm_clk_s PORT sys_rst = sys_bus_reset END

BEGIN dsbram_if_cntlr PARAMETER INSTANCE = docm_cntlr PARAMETER HW_VER = 3.00.a PARAMETER C_BASEADDR = 0x80800000 PARAMETER C_HIGHADDR = 0x80801fff BUS_INTERFACE DSOCM = docm BUS_INTERFACE PORTA = dsocm_porta END

BEGIN bram_block PARAMETER INSTANCE = dsocm_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = dsocm_porta END

BEGIN plb_v34 PARAMETER INSTANCE = plb PARAMETER HW_VER = 1.02.a PARAMETER C_DCR_INTFCE = 0 PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_bus_reset PORT PLB_Clk = sys_clk_s END

BEGIN opb_v20 PARAMETER INSTANCE = opb PARAMETER HW_VER = 1.10.b PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_bus_reset PORT OPB_Clk = sys_clk_s END

BEGIN plb2opb_bridge PARAMETER INSTANCE = plb2opb PARAMETER HW_VER = 1.01.a PARAMETER C_DCR_INTFCE = 0 PARAMETER C_NUM_ADDR_RNG = 1 PARAMETER C_RNG0_BASEADDR = 0x40000000 PARAMETER C_RNG0_HIGHADDR = 0x400000ff BUS_INTERFACE SPLB = plb BUS_INTERFACE MOPB = opb PORT PLB_Clk = sys_clk_s PORT OPB_Clk = sys_clk_s END

BEGIN opb_uartlite PARAMETER INSTANCE = RS232 PARAMETER HW_VER = 1.00.b PARAMETER C_BAUDRATE = 9600 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_CLK_FREQ = 100000000 PARAMETER C_BASEADDR = 0x40000000 PARAMETER C_HIGHADDR = 0x400000ff BUS_INTERFACE SOPB = opb PORT OPB_Clk = sys_clk_s PORT RX = fpga_0_RS232_RX PORT TX = fpga_0_RS232_TX END

BEGIN dcm_module PARAMETER INSTANCE = dcm_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLKFX_BUF = TRUE PARAMETER C_CLKFX_MULTIPLY = 3 PARAMETER C_CLKIN_PERIOD = 10.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_CLKDV_DIVIDE = 2.0 PORT CLKIN = dcm_clk_s PORT CLK0 = sys_clk_s PORT CLKFX = proc_clk_s PORT CLKFB = sys_clk_s PORT RST = net_gnd PORT LOCKED = dcm_0_lock PORT CLKDV = ocm_clk_s END

Reply to
Joey
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Did you verify all the designs actually meet the desired timing constraints? Check out the *.twr and *.par files in the implementation directory.

Paul

Joey wrote:

Reply to
Paul Hartke

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