=_NextPart_000_0029_01C3A95C.F07B3E80 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Good day gents, I am wondering if VHDL (or Verilog) code exists = in order to make a frequency doubler in a normal CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric = duty cycle. Below some code can be found which generates a by-2 multiplied frequency =
- however the duty cycle is very assymmetrical ...
Many thanks for your input !
Regards,
Michel