I feel it is better to start a new thread, I have compiled my divide oscillator clock by ten module, what do I do now?
//////////////////////////////////////////////////////////////////////////// ////// module clkdiv10mod(in, out); input in; output out;
reg [3:0] cnt;
always @ (in) begin cnt=cnt+1; if (cnt ==9) begin cnt =0; cnt =!cnt; end end
endmodule
Here is my console output:
=========================================================================
- HDL Compilation * ========================================================================= Compiling verilog file "clkdiv10mod.v" in library work Module compiled No errors in compilation Analysis of file succeeded.
=========================================================================
- Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for module in library .
Building hierarchy successfully finished.
=========================================================================
- HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis.
=========================================================================
- HDL Synthesis * =========================================================================
Performing bidirectional port resolution...
Synthesizing Unit . Related source file is "clkdiv10mod.v". WARNING:Xst:647 - Input is never used. WARNING:Xst:1306 - Output is never assigned. Found 4-bit adder for signal . Summary: inferred 1 Adder/Subtractor(s). Unit synthesized.
========================================================================= HDL Synthesis Report
Macro Statistics # Adders/Subtractors : 1 4-bit adder : 1
=========================================================================
=========================================================================
- Advanced HDL Synthesis * =========================================================================
========================================================================= Advanced HDL Synthesis Report
Macro Statistics # Adders/Subtractors : 1 4-bit adder : 1
=========================================================================
=========================================================================
- Low Level Synthesis * =========================================================================
Optimizing unit ...
=========================================================================
- Partition Report * =========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
------------------------------- WARNING:ProjectMgmt - "C:/Xilinx/clkdiv10/clkdiv10mod.ngc" line 0 duplicate design unit: 'Module|clkdiv10mod'
Process "Synthesize" completed successfully
Command Line: C:\Xilinx\bin\nt\ngdbuild.exe -ise c:/Xilinx/clkdiv10/clkdiv10.ise
-intstyle ise -dd _ngo -i -p xc9500 clkdiv10mod.ngc clkdiv10mod.ngd
Reading NGO file 'c:/Xilinx/clkdiv10/clkdiv10mod.ngc' ... Loading design module "c:\Xilinx\clkdiv10/clkdiv10mod.ngc"... WARNING:NgdBuild:578 - Design contains no instances.
Checking timing specifications ... Checking Partitions ... Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 1
Writing NGD file "clkdiv10mod.ngd" ...
Writing NGDBUILD log file "clkdiv10mod.bld"...
NGDBUILD done.
Process "Translate" completed successfully
Started : "Fit". ERROR:Cpld:1005 - Design 'clkdiv10mod' has no outputs.
Process "Fit" failed