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Frequence max: many question from a beginner

Hi

1) how could I have the worst delay path in xilinx ise in a design? Because if i put a timing constraint it give me the worst paths if the constraints is not reach but if the constraint have been met we haven't the worth path.

2) When can we say that we have reached the max frequency possible for the design? In my mind it 's for when we made an IP with no timing constraint when can we say that we are fast enought?? Relative to time due to logic and route , when we have more time due to route than logic or something else??

3) Is it possible to put a part of the a design out of timing analyze? because a part of my design is only here for simulation (it generates stimuli when onboard) and the worst delay path is due to this part. Or should I analyze each part of my design separately without the test part??

Thanks for your answers

Regards

Alexis

Reply to
KCL
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"KCL" schrieb im Newsbeitrag news:421b902b$0$3103$ snipped-for-privacy@news.wanadoo.fr...

the

Timing Analyzer is your friend. Tell him to check against tighter constraints, and it will show you the failing paths.

and

Again, timing analyzer is your friend. It will tell you exactly how much time is spent in logic and routing.

Yes, you can exclude paths/parts from timing analyze. But why? Tell the analyzer the real clock frequency of each part an everything is fine. Even just for testing/simulation/emulation, you test logic must be fast enough.

Regards Falk

Reply to
Falk Brunner

Yes I found it, I use verbose report and that allright

But what I wanted to know it is in the cese of making an IP(take DSP IP for example) when can we say that all effort we will do will be useless to get a better frequency??that we reach the max frequency possible?? Is there a criteria?? like being at 80% of the max frequence limit of the device or having worst path with only 2 or 3 level logic???

At the start I added some stuff to make input for my design: a 25 bits counter to slown down refresh frequency of the push button and that was this counter that was the worth path so I finnaly decided to delete it from my design and make a top that include my design as component and this counter.

All this are in fact only for educative , this project permit to me to discover a lot of tip about foundation and making design running faster

Regards

Alexis

Reply to
KCL

"KCL" schrieb im Newsbeitrag news:421cf072$0$11683$ snipped-for-privacy@news.wanadoo.fr...

for

get

To answer this question, you need experience. Then you know the critical points of a design and the target technology. Lets say for Xilinx the BRAMs are slowr than FlipFlops. SRL16 is also slower than normal FlipFlops. Similar things apply to other devices from other vendors. Routing is also a issue.

Regards Falk

Reply to
Falk Brunner

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