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How can we do FPGA VHDL Verification faster and with better quality ?
? at no extra cost?

This is actually possible ? and with an average efficiency improvem
ent of 20 to 50% for medium to high complexity FPGAs. Less for data path or
iented designs and more for control or protocol oriented designs. At no ext
ra cost.

All that is required is that you do your testbench development the same way
 you do your design. Every single FPGA designer knows that a good top level
 design architecture is critical. Most FPGA designers also know that a good
 microarchitecture is at least as important for module design. It should th
us be obvious that a good architecture is also equally important for your t
estbench, but for some strange reason most testbenches do not have the same
 good architecture as the design being verified.

Most designers agree that the following are critical for an efficient devel
opment of a high quality design module:
- Overview, Readability, Simplicity
- Modifiability, Maintainability, Extendibility
- Debuggability
- Reusability

So why should testbenches be any different, with on average the same time u
sage as the actual design?

It should be obvious that these aspects are equally critical for testbench  
development, but there has been no standard solution to build a good testbe
nch architecture ? until now ? when UVVM has been introduce
d as a free and open source solution to this challenge.


http://www10.edacafe.com/blogs/aldec/2016/11/14/fpga-vhdl-verification-can-
we-do-this-faster-with-better-quality-at-no-extra-cost/

And please join the webinar tomorrow by registering at either of
https://www.aldec.com/en/events/770 for presentation at 3pm CET
https://www.aldec.com/en/events/771 for presentation at 11am PST


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