dear all
Let me put a few questions....
During reading XAPP151, the length of frame (Xilinx Virtex) is unclear for me. (2 IOB each 18 bit, each CLB 18 bit ---> then how many CLB in each frame, and how long is each frame?....
2nd thing is how many padding bits are attached into each frame?3rd thing unclear is the addressing .... it will be great if there is document (or web) which comprehensively explains how the addressing (via frame) works...
Thankyou from fpga novice