dear all
Let me put a few questions....
During reading XAPP151, the length of frame (Xilinx Virtex) is unclear for me. (2 IOB each 18 bit, each CLB 18 bit ---> then how many CLB in each frame, and how long is each frame?....
2nd thing is how many padding bits are attached into each frame?3rd thing unclear is the addressing .... it will be great if there is document (or web) which comprehensively explains how the addressing (via frame) works...
Thankyou from fpga novice
cite xapp151 p.5: "The number of configuration bits in a frame is 18 × (# CLB_rows+2)... " # CLB_rows depends on which (virtex)device you are using... see Table 3 in xapp151.
cite again xapp151 p.5: "...and is padded with zeroes on the right (bottom) to fit in 32-bit words."
well, besides it is only for virtex (until now! update to xapp138 is announced maybe some updates to xapp138 will appear there) xapp151 is not that bad, maybe you should spend some more minutes reading it...
simon
You can use JBits (
Miguel Silva
The introduction to the following paper by Li and Hauck might help with your high level understanding of the configuration architecture:
There are 48 frames in a column, with the size of a frame dependent on the number of (CLB) rows in the device. I'm not aware of any documentation on the mapping between individual resources (e.g. a LUT's content) and the configuration bitstream. As suggested by the previous poster, delving into JBits is probably your best option.
Irwin.
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