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FPGA with ASIC FPU units

SRC are talking about the following characteristics for a field-programmable floating-point device that they intend to put in one of the variants of their SRC-7 reconfigurable computer:

Hard floating point units with field-programmable interconnect

50 DPFP mults and adders per chip -> 30 GFLOPS >100 SPFP mults and adders per chip -> 60 GFLOPS

Each FP unit also performs 53 or 24 bit integer ops with 106 or 48 bit results

Selectable 150 MHz or 300 MHz operation

I've heard that these units will have single-cycle latency. I don't imagine that these FPGAs will be cheap as there must be considerable NRE costs that won't be recouped so easily as they would be for a Xilinx chip. However, they open up a whole new world of possibilities for scientific computing, making double-precision much more viable than it has been previously.

Is this the device reconfigurable computing has been waiting for?

Reply to
Robin Bruce
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Not really. I remember 25 years ago there was a Weitek FPU to be had external to a cpu. Even though it was much faster than the 8087, the 8087 won, especially after it was integrated into the 80386.

Now, you can make your own FPU with an FPGA. You can define where you want the silicon spent on. Everything single cycle may not be optimal, it may be overkill. Rather have certain stages pipelined but have three FPUs instead.

Rene

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Reply to
Rene Tschaggelar

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