FPGA vs ASIC area

Rick,

see below

Aust> aust>

I will discuss it with Peter. As well, I have no shortage of folks who email me directly or on this board to let me know if they do not like a posting.

He tells me you are a valuable asset to this group because

Untrue. I have only been at Xilinx for 6 years, before that I spent 26 years in the telecom business. What I know about ICs and FPGAs has been gained from 6 produt releases. There are many at Xilinx with many many more years, and products, under their belts than I. I consult them for my responses, as I by myself, am nothing.

But your BS is enormous.

No need to be insulting.

This comment

I have not heard this feedback. Let me know who you contacted. It is important to me that all feedback get back to the people who should hear it.

I don't know if this ever makes

I am sorry if I have offended you in any way. I have no idea what I have done.

My managers are well aware of my postings, as well as what people say about me. If there is something you feel they should know, email me directly and I will give you their email addresses so you may reply in private to them. Or post it here.

If you wish, I can be reached directly by this email address. I am always willing to listen to how I can improve.

Reply to
austin
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MK,

Unfortunately, I do not. My information was from word of mouth from IC designers that worked at Intel, but are no longer there.

It counts every single FF added for capture, scan chain, as well as all test loopbacks, multiplexers, etc. that are added for any reason that is not purely functional.

I know that there is not that much area added to the IBM 405PPC, and not that much added to the MGT, etc. but the Pentium is much more complex, and may require more logic for test reasons to get better coverage.

If I find a reference, I will post it.

As I said to Rick, I really don't know all that much, but I am a good listener. And when I listen to IC designers talk about what they did, and so forth, I do remember what they say.

Aust> >

Reply to
austin

How long it takes to run the tests is one thing, how long to design the tests is another. For a small volume ASIC the design (human) time could be long amortized over the chips produced.

-- glen

Reply to
glen herrmannsfeldt

Glen,

One potential advantage we have is that we have been doing this for 20 years, and testing the interconnect, FFs and LUTs doesn't change that much from generation to generation.

Same could be said for an ASIC cell that has been used for the last few generations, too (as long as it hasn't changed much).

The overall ASIC functional test vectors are often quite complex.

That leaves time to get clever with paterns.

Aust> aust>

Reply to
austin

This is a blatant lie (plus a breach of confidence). I had only asked Rick to make peace with Austin, and accept the fact that he has a different style than mine.. Nobody will push a wedge between me and Austin. We are neighbors, partners, and friends, and complement and help each other every day in many ways.

This thread seems to have run its course. The original question about the area ratio between ASICs and FPGA was (as I wrote) meanigless and cute. Which one is smaller, uses which process, and takes how long to test is all reflected in one single number, the price charged by the vendor. And there is intense competition which keeps us all on our toes...

The user (that is most of the people in this newsgroup) should only be interested in cost, performance, power consumption, design effort, reprogrammability, time to market, availability, and general risk. Smart engineers will know how to make a rational choice.

ASICs will be the right choice sometimes, FPGAs will be the right choice in most cases. But we know that in spite of less than 2000 new ASIC designs worldwide per year(!), the high-volume ASIC business is still much larger than the FPGA business. That gives FPGAs a tremendous opportunity to grow. We like that!

Peter Alfke

Reply to
Peter Alfke

rickman,

As one of the many people that see the convesations back and forth between the two of you, please consider that you *may* be predisposed to consider Austin's comments as argumentative.

It is the view of this engineer that Austin's behavior on this board is very professional and only suffers occasionally from the frustrations of the inability to communicate clearly what he knows whether due to the limitations of written communications or the receptiveness of the audience.

Please try to make your points, not argue them. It's typical of your posts to others to be informative as it is with Austin's. If either of you come to a post by the other as a challenge to his manhood, the conversation won't be productive for anyone.

It takes two to tango.

Respectfully, John_H

Reply to
John_H

Which is it, a lie or a breach of confidence??? Besides, I don't recall you asking that I keep it a secret. You just asked me not to argue with him.

Perhaps I didn't get the words exactly right, but you acknowledge the concept. My point was that even you understand that he goes beyond the norm in his posts.

No one is trying to spilt you two up. You can sit next to each other as much as you want.

Yes, that is the opinion I have stated exactly. The end user does not care about the details of how results are obtained since there are far too many details for any one to be an indicator.

--
Rick "rickman" Collins

rick.collins@XYarius.com
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Reply to
rickman

Do you recall the post I responded to? Austin is prone to making personal comments bordering on redicule. His "technical" points often come off as posturing rather than rational discussion. My beef with Austin is that he refuses to acknowledge (or is unable to understand) these points.

That is right. Did you make the same comment to Austin?

--
Rick "rickman" Collins

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Reply to
rickman

Honestly, no. To me, you appear to be the one predisposed to being argumentative in the posts back and forth. The usenet does not allow a "proper" form of factual documentation that is typically left to footnotes or bibliography in industry journals and academic papers. The statements made by any individuals on this forum as "fact" should be taken by the reader with a grain of salt. Caveat emptor and all that. I think most readers realize that if you read it on the internet it isn't *necessarily* true.

Even the most informed people with the best of intents will not have a complete documentation trail back to the origins of their knowledge.

It seems that if this trail is not stated, you're assuming that Austin - as opposed to any typical poster - is "talking out of his hats."

This is my view.

I do notice that Austin may get frustrated by people stating that he's wrong about what he posts, probably half of which comes from rickman. In the previous post I did mention the frustrations as being the only detractor from complete professionalism and I'm assuming that that comment is being considered in the whole of his usenet experience. Personally, I don't consider it a negative at all. Stubbornness is tough for me to deal with as well.

Reply to
John_H

I have the same feelings as John.

Take it easy Rick! You don't need to agree to Austin, but you really crossed the line when you started to offend him.

Remember, we are not discussing religion!

Luiz Carlos.

Reply to
Luiz Carlos

I think we all understand that Peter likes banging the FPGA drum -- but the real relevence of the area difference is nothing to do with price/flexibility/design effort/time to market/risk, it's power consumption and often total number of chips/packages, which are directly linked to the silicon area inefficiency of FPGAs compared to ASICs.

The inescapable fact is that an FPGA solution will always consume a lot more power than an ASIC solution in a similar technology, typically 10x higher. For applications where this matters an FPGA solution is often just not viable; examples include portable equipment where 5-10W for an FPGA rules it out compared to 0.5-1W for an ASIC, or high-complexity system application where we're comparing 5-10W for a single big ASIC with 50-100W for 5-10 big FPGAs.

For either of these types of application FPGAs will never catch up with ASICs -- and before anyone says "ah, but FPGA power goes down with improving technology", so do ASICs, and all that happens is that the complexity of the systems expands to use the increased processing power available i.e. the chips don't shrink!

One implication of this could be that the "China Syndrome" problem (increasing power density per mm2 as technologies shrink and clock rates increase) will actually reduce the chances of FPGAs addressing these applications.

And if the major end use application of silicon switches from mains-powered equipment to portable (as some market surveys predict) FPGAs could even migrate back to being used for prototyping only...:-)

Ian

P.S. Of course price and so on matter -- but would you buy a mobile phone nowadays whose battery weighed a pound, however cheap it was?

Reply to
Ian Dedic

For the huge system applications, however, there are cooling solutions (eg, IA64 heatsinks which are rated for 140W of power) which work, so the cooling cost can get just added onto one more side for the asic and against the FPGA, to balance out that $1M mask set.

But portable will never be a strong suite of conventional SRAM-based FPGAs: programmable interconnect is simply too much capacitence compared with wires, and thats an ugly fact of life for dynamic power (let alone the static power of all those SRAMs).

--
Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu
Reply to
Nicholas Weaver

I'd have to side with Rick on this one - Austin's 'bad hair day' comment is what prompted Rick's response.

Personally, I can easily ignore Austin's marketing spiels.

My real beef with Austin is when he flames up an accurate technical post with an insult-and-opinion laden response, for no apparent reason other than to spread FUD when someone has taken the time and effort to document tool or device problems about which Xilinx has been less than forthcoming.

He makes lots of noise when you point out the flaws in his reasoning, yet when you pin him down by asking a detailed technical question, he becomes strangely silent.

Brian

Reply to
Brian Davis

I appreciate your comments. I am sure I would do better by not making noise about these things and normally I let it slide. But sometimes Austin gets under my skin.

So I would like to apologize to all and I promise to restrain myself in the future. I have had enough "conversations" with Austin to realize that he is not going to change his "style" of posting here, so I would do better just to leave it all alone.

Besides, this is just the internet... pretty silly to do much arguing here.

--
Rick "rickman" Collins

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Reply to
rickman

The concept of wasted power is not relevant... unless its a walkman strapped to your arm... I don't see many joggers with heatsinks strapped to their backs :-)

But I did read a thesis on a 'self-timed' gate array design where everything is done by handshakes and local clocks. This would be imposable in a FPGA with its 4 clocks and no support for handshaking with variable delays.

I've seen quotes of 30% smaller die and 30% lower power.. but you have to take marketers at their word don't you?

Imaging a MP3 player where only the gates being used are being clocked and even then... only at the rate they are being used! You are talking an increase in play time and the saving of those batteries ... its even good for the environment.

I wouldn't be surprised if things like MP3 and small consumer goods before the main stay of gate arrays.. they are one of the few things where this kind of benefit can be justified. but in a society of waste and consumerism ... power isn't worried about ... (unless you live in California).

And this is not fantasy.. google knows all about it :-)

Simon

Reply to
Simon Peacock

Agreed for systems where forced-air cooling (or enormous heatsinks!) are OK. If your system is one PCB is a sealed box you're in big trouble :-)

Exactly what I was saying as a counterpoint to the Xilinx "FPGAs will take over the world" point of view! In the functions-per-mW game ASICs will always win.

Ian

Reply to
Ian Dedic

You don't necessarily have to use async logic to achieve this. Fine grained clock-gating can get you most of these power savings, but this is something that so far can only be done in an ASIC.

However, as far as battery operation is concerned, for quite a few applications it's not so much the dynamic power that is a problem, but the huge static power consumption of FPGAs. Here we talking the difference between a FPGA running for a few hours, compared to an ASIC running for a couple of years.

Cheers, JonB

Reply to
Jon Beniston

Brian,

I respect you opinion, but I do not agree with you ('insults and opinions' & FUD?).

I have never been silent on an issue.

I have been wrong, and admitted it on occasion.

And, I believe I have been right, and had folks disagree with me.

But never silent.

Aust> John H wrote:

Reply to
Austin Lesea

Here is an IBM + Xilinx paper on comparisons of ASIC vs FPGA. Note that, this paper probably gives conservative numbers (since Xilinx co-authored it).

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I have found that in general (the exact answer depends on speed you are running at etc), all three metrics of area, power and speed are off by 50 to 100x. For example, several FPGA dies are 100 sq.mm. And you can fit about 1 million gates on them. At the same technology node, you can fit about 100 million gates or more (especially if you are Intel/custom designers).

To add to the discussion about Structured ASICs (SAs) vs FPGAs vs ASICs that took place on this thread, SAs save on NRE costs and some backend tools costs over ASICs. But all other costs, designing, verification, and testing are the same for all three, SAs, FPGAs, & ASICs. The reason why people feel that FPGAs take lower time to design and deploy is because of the size of designs you can fit on a FPGA. Don't be fooled by the "system gates" that FPGA vendors tout. In reality, those system gates should be divided by 5 to 10 depending again on what speed you are running your design at. This means that a 8million system gate device can fit less than 1 million ASIC gates for high performance designs and about 2 million ASIC gates at very slow speed.

In as far as mask costs and when it makes sense to use FPGAs or SAs instead of ASICs can come down to a simple Excel sheet that has your design, verification, CAD tools etc cost for each (pretty much the same for all three, except for back-end tools) + the NRE costs for each ($0 for FPGAs, $100K-250K for SAs, $0.6-0.8M mask costs at 0.13u for ASICs) and the cost per chip (very high for FPGAs, lower for SAs and super low for ASICs) times the volume. (Hope that was not too much of a ramble).

Of course, the folks from Xilinx & Altera on this board might/will disagree with me -- but this is just one man's opinion based on talking to a lot of FPGA designers and also, some inside info from marketing folks at Xilinx & Altera ...

Sumit

Reply to
SG

Here is another article that has comparisons of ASIC vs FPGA area. This is from Charles Rupp, who knows FPGA architectures inside out:

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Sumit

Reply to
SG

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