FPGA timing

Hi, I am porting my design from ASIC to FPGA, but I found the timing in FPGA is very bad. What I konw is to set up the clock constraints, I don't know how to add other constraints. Can any boby give me some hints? thanks very much. I use Altera clone II.

skyworld

Reply to
skyworld
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Pipeline the design. Pay attention to the amount of combinatorial logic between registers.

Reply to
Ray Andraka

skyworld schrieb:

Learn the FPGA architecture and restructure your code to make it easier to map to it. For example most architectures have a LUT - carry logic - DFF chain.

If you write somethin like if add then result = a + b; else result = a - b; end if;

You must be extremely lucky with the tools to get less than three luts per bit with a critical path of two LUTs and a carry chain.

If you write: if add then temp = b; else temp = -b; end if; result = a + temp;

you need only one LUT per bit and the critical path is one LUT plus a carry chain.

This is because the MUX is in front of the carry logic now and can be implemented in the same LUT as the non carry logic of the adder.

There are more areas like these were you can make your design easier for the tools to optimize.

Kolja Sulimma

Reply to
Kolja Sulimma

Hi Ray & Kolja, thanks for your reply. The advice is very helpful, but the question is that the code is for ASIC design and is frozen. I just migate the code to FPGA to check its function. So do you have any suggestion on how to setup constraints? something like DC do in ASIC design? thanks

best regards

skyworld

Kolja Sulimma wrote:

Reply to
skyworld

skyworld schrieb:

Usually ´the actual performance of the design can not be improved much compared to the results optained by a simple clock cycle constraint. However, often a static timing anaylsis reports an overly pessimistic timing. You can get get better and more realistic values if you specify false paths and multi cycle constraints to relax the timing budget.

You can perfom the modifications that I suggested and use an equivalnce checker to proove that you did not change the behaviour of the circuit. That is a risk free approach for a frozen desing. The particular transformation that I described also reduces ASIC circuit area and power consumption.

Kolja Sulimma

Reply to
Kolja Sulimma

If you are just checking functionality, why are you concerned about timing? Reduce the clock rate and check the functionality, if that is what you intend to do. But you must be concerned about clock distribution (use only global clocks!) otherwise you invite ugly hold-time issues. Peter Alfke, Xilinx

Reply to
Peter Alfke

If you are using Quartus II V6.0 Full Edition, you may want to take a look at the new TimeQuest Timing Analyzer. Assuming your ASIC had an SDC file with timing constraints (e.g. from DC Compiler), you should be able to use it if you only map the signal names (e.g. ports, pins and cells) to the Quartus names. You may want to check the following link:

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If you don't have access to V6.0 Full Edition, you can still use the Classic Timing Analyzer and do a lot of the same constraints, only you will have to learn a different constraint format and some of the differences between the Classic Timing Analyzer and a Timing Analyzer like PrimeTime. For more help on the Classic Timing Analyzer, check:

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Hope this helps.

-David Karchmer Altera

Reply to
dkarchmer

Did you not put any timing constraints on the design? If so, then you need to review the user's guide on timing constraints and add them to the design. Note however, that timing constraints just tell the tools what you require the timing to be. It doesn't mean the tools will be able to place and route the design to meet your timing constraints. If you already have the timing constraints on the design, then you need to start digging into the design to find out where the failing paths are, and address those paths either by relaxing constraints, hand placing and possibly hand routing them, or by revising the logic to reduce the number of combinatorial levels the signal has to pass between flip-flops. For high fanout signals, you can also consider duplicating logic to reduce the fanout. In general, you are not going to achieve ASIC speeds with an FPGA without carefully crafting your design to the FPGA architecture. An ASIC design dropped into an FPGA with no changes will never meet the potential performance of the ASIC implementation of the design if done on a feature size similar to that of the FPGA.

Reply to
Ray Andraka

Ray,

Your response below appears to imply that you have been able to achieve ASIC performance with FPGA implementations. As this goes against my intuition, could you elaborate?

I assume you would be comparing an ASIC implemented in a larger, slower process to an FPGA in the state-of-the-art process?

Thank you, Stephen

Reply to
stephen.craven

What I am trying to say is that the performance will fall far short of the ASIC if you try to use the same design with an FPGA as you use with the ASIC. The only way to get even close is to design to the FPGA architecture, and that means heavily pipelining the design, limiting logic ore or less to 4 input functions, and taking advantage of FPGA macro structures like the memory and multipliers. The majority of the ASIC designs I have seen have far too few pipeline stages to be able to use the FPGA near the top of its performance envelope. Many if not most of those have targetted ASIC performance that is within the means of an FPGA of similar vintage, but that won't happen without completely redesigning it with the FPGA architecture in mind.

Reply to
Ray Andraka

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