FPGA Synthesis to LUT: Looking for papers/algorithms

Hi,

I am looking for some easy to understand papers/links that explain the mapp ing from a generic netlist to LUT. For e.g. looking at c=(a+b)*c - d; I w ould imagine there is a generic adder, multiplier and subtractor involved a nd I understand that Verilog/VHDL -> generic synthesis process.

From the generic netlist , say a collection of and/or/nand/not OR higher le vel macros like multipliers etc how do you map to the FPGA LUT? Some papers or links would be very helpful.

Thanks

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Fpga Newbie
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Hi,

I agree, there isn't much papers and links on this subject.

I recently came across this:

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You can also search for relevant Xilinx/Altera/Tabula patents in Google Patents.

Thanks, Evgeni

Reply to
OutputLogic

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