FPGA synthesis problems

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
Dear Helper,

I am currently a student at The Nottingham Trent University and
carrying out a project using an Actel 1280XL FPGA and Mentor Graphics
tools.

I have created a VHDL model purely using a behavioural architecture
using MGC Design Architect.
I then applied this model to Actel's ACTMap which is used to convert
the VHDL model into a netlist, a *.edn file and *.aml file is
successfully created.

I then apply this netlist to Actel Designer. In Designer I can compile
the netlist, place the pins using the PinEdit, after this I can then go
on to layout the design. Once the layout has been completed I can then
use the 'Extract' button to create a *.sdf file from which a timing
file is created.
The problem occurs when I apply back annotation and try to simulate the
design with the *.sdf file. I apply the .sdf to QuickHDL by using the
following in the command prompt: -
                    qhsim <design> -sdf<delays> <SDF file>

This will load up QuickHDL and then errors will occur, The errors are
as shown below:

ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'INBUF_7'
ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'MX_3'
ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'MX_3'
ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'INBUF_1'
ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'OUTBUF_10'
WARNING: home/biggc/fat.sdf: this file is probably applied to thw wrong
instance.
Ignoring subsequent missing instances from this file.
Failed to find any of the 8 instances from this file.
The file is probably intended for a lower-level instance, not the
top-level.

When the VHDL model has been applied to Actel Designer, the code is
converted into a circuit, i.e. I/O pad buffers are created etc. this is
what the errors seem to be referring to as I assume its trying to
simulate the VHDL code which doesnt contain these instances. Do I need
to simulate the .edn file (the netlist file) as well as the .sdf file?
and if so how do I achieve this?

The version of design manager I am using is Design Manager V8.6_2.1.

I hope I have explained the problem clearly so that you can understand
what is going on?

Thankyou for your help. Please feel free to contact me at any of the
following: -

snipped-for-privacy@ntu.ac.uk
snipped-for-privacy@yahoo.co.uk

Kind regards

Gavin Biggs
CA204080 (Uni Username)
BEng (Hons) Electronics & Computing
The Nottingham Trent University


Re: FPGA synthesis problems

Quoted text here. Click to load it

Consider running a vhdl simulation on
your model. Once this is working
as you expect, run a trial synthesis
and static timing analysis.

      -- Mike Treseler

Site Timeline