Run it through the mapper. The mapper will give you a report.
be
Run it through the mapper. The mapper will give you a report.
be
Hi
I've done a design in VHDL using the XILINX software and I was wondering, how can I tell how much of the FPGA my design uses? I was hoping I would be able to find out what percentage of the FPGA my design uses.
Thanks,
specifically, check the file with the suffix .mrp in your synthesis directory.
-- Regards, John Retta
email : snipped-for-privacy@rtc-inc.com web :
wondering,
would
Fitter (place&route) will tell you. Report looks like:
Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used
39 /72 ( 54%) 337 /360 ( 94%) 38 /72 ( 53%) 4 /34 ( 12%) 140/216 ( 65%)look at the synthesis report (of throught the floorplanner)...
be
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