1) title blocks on schematics ... Xilinx authorship/ownership 2) Reference manual ... Xilinx authorship/ownership 3) PCB artwork ... Xilinx authorship/ownership 4) Search RM for Digilent ... reference only compatability with Digilent boards.
The unit does have Digilent compatable I/O ports, and may well have been designed under contract for Xilinx, but that does make it a Xilinx labeled Product that they claim ownership of, no matter who is building it for them. In fact, everything suggests it's actually a Xilinx Research Labs design instead ... specifically using Digilent I/O connectors for the University Program, to make it compatable with student board projects.
And yes, I did finally find the statement on the bottom of page 67 in the reference manual which starts "the SATA specification requires an out of band signalling state that is to be used when the channel is idle. ... "
Which means that since this is REQUIRED, and not provided the serial interfaces are NOT SATA, but simply have the same data rates and encoding ... not SATA which is a full system level specification. Using SATA everywhere to describe the interface, and not meeting the specification is simply bait and switch, substituting the Xilinx bit serial interconnect in it's place which just happens to be a non-compatable subset of the SATA standard.
A parallel 16 bit data bus with control signals is not SCSI, unless it at least is capable of operating with the complete SCSI protocol ... anything short of that, and it's SASI, Pertec, or some other 16 bit bus, maybe even 16 bit ISA/EISA.