When you say it works well when simulation do you mean that you have done a back-annotated simulation or just your rtl simulation. Back annotated simulation is where you take the .vo file from quartus (verilog output) and the SDF file generated by quartus (the file with all the actual delays) and simulate that design and see if it works as expected. Of course the better way is to put in good timing constraints and do a thorough timing analysis which ensures that you are catching all timing errors not just the ones which appear for your specific simulation.