FPGA ROUTING

Hi everyone: I am new to FPGA and looking for a possible topic on FPGA routing algrithm. I read some classic articals in this field and find that when people are talking about routing algrithms (i.e. pathfinder) they generally ignore the architecture of switch box, while it is said that the topology of swich box may have an impact on the routability on the router. Thus, I am wondering how the router determine the path inside the switch box? And I am thinking is it possible to add the routing cost on the switch box to the cost function to the pathfinder algrithm?

I am totally new to the FPGA and its routing. I hope the above question may not be so naive. And I am still not sure which topic in this area is worthy to do. I appreciate if anyone give me some advice.

Thanks and happy new year.

Ruiz TAMU

Reply to
Ray
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Reply to
Peter Alfke

Hi Peter: Thanks for your reply. Do you mean there is not much to do in the FPGA routing? I have some interests in FPGA and hope to work in this field in future. But I am not sure which topics people are working at in this field nowadays. (Or which topic may help me find a good job in this field when I graduate.) The lab I am in is mainly concerned with VLSI algorithm, that is why I first looked into the routing algorithm in FPGA. Can you please give me some advice or show me where to find such kind of infomation. Thanks

Ruiz.

Reply to
Ray

Perhaps you are familiar with the VLSI EDA "DAC" conference, I used to go to it eons ago (when FPGAs almost didna exist yet), since then they must have presented a few papers on FPGA EDA too. Check out this and other conferences in the FPGA, EDA field start with IEEE or ACM.

Also if you visit the DAC website or go to one of the shows floor exhibits you can see who the hardware vendors are for accelerating EDA, usually with the most expensive FPGAs hidden in big box, some of them must be still around, used to be lots of them.

Also just google back through this NG, this question pops up regularly.

John Jakson

Reply to
JJ

FPGA in BGA running at hight frequency is quite a challange to route (I'm talking about more than 484 balls package). The first important step is to assure a correct grid and route thickness. The second one is to place manually via on pad according to the required padstack. And the third is to choose right the power supply filtering capacitors and/or high capacitance supply laminate core (as ZBC1000 or ZBC2000) and all the routes impedances. I suggest you a deeply visit on the following site:

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and of course browsing the email topics on the forum.

greetings, Vasile

Ray wrote:

Reply to
vasile

OK, this is about routing outside the FPGA, sorry.

vasile wrote:

Reply to
vasile

Hi Vasile, Good link! As you say, I think the OP meant something else, but thanks for this! I'll add it to the RoHS BGA thread. Cheers, Syms.

Reply to
Symon

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