1. Home
  2. Field-Programmable Gate Arrays
  3. FPGA Reconfiguration : Virtex-4 Frames

FPGA Reconfiguration : Virtex-4 Frames

Hello everybody,

I'm working on dynamic partial reconfiguration of Xilinx Virtex-II FPGAs. In all Virtex-Device-Families the smallest (re-)configurable unit is a FRAME. I know that in Virtex and Virtex-II, these Frames are running from the top of the device to the bottom. This means that during reconfiguration of a module in the center of the device, no signals can get from the left side to the right side.

I heard that in Virtex-4, frames didn't go from the top of the device to the bottom but, that there were upper and a lower frames which could also be addressed separately. This would be helpful, concerning the problem described above. Unfortunately I didn't find any information on this topic in the Xilinx Data Sheets.

Now, my question is: Are there upper and lower frames in a Virtex-4? Or do Virtex-4 frames look like the frames in Virtex and Virtex-II?

Thanks in advance Andreas

Reply to
Andreas Nett
Loading thread data ...

all Virtex-Device-Families the smallest (re-)configurable unit is a FRAME. I know that in Virtex and Virtex-II, these Frames are running from the top of the device to the bottom. This means that during reconfiguration of a module in the center of the device, no signals can get from the left side to the right side.

bottom but, that there were upper and a lower frames which could also be addressed separately. This would be helpful, concerning the problem described above. Unfortunately I didn't find any information on this topic in the Xilinx Data Sheets.

Virtex-4 frames look like the frames in Virtex and Virtex-II?

The height that a frame covers is a clock region, and the number of regions depends of your V4 size.

You'll find additional infos on the dedicated mailing list:

formatting link

Don't loose time with the tools: it is said that ISE 8.1i will address this issue with V4, but yet I've seen no date of availability. Anyone?

Reply to
Stephane

formatting link

page 69 (1312 bits, of which 12 are the FRAME_ECC syndrome), and continuing

and

formatting link

So a larger device has a number of vertical frames (not just two).

Aust> Hello everybody,

all Virtex-Device-Families the smallest (re-)configurable unit is a FRAME. I know that in Virtex and Virtex-II, these Frames are running from the top of the device to the bottom. This means that during reconfiguration of a module in the center of the device, no signals can get from the left side to the right side.

bottom but, that there were upper and a lower frames which could also be addressed separately. This would be helpful, concerning the problem described above. Unfortunately I didn't find any information on this topic in the Xilinx Data Sheets.

Virtex-4 frames look like the frames in Virtex and Virtex-II?

Reply to
Austin Lesea

Hi Austin,

when are we to expect 8.1i ?

BR

Aust>

formatting link

Reply to
Stephane

Stephane,

formatting link

is a new version of the web power tool, but for the full ISE 8.1i, I think that is still yet to be announced ... soon.

Aust> Hi Austin,

Reply to
Austin Lesea

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.