FPGA Reconfiguration Question

I wanted to give you more information..

I have an application that I can implement on a Virtex device by Partial Run Time Reconfiguration (RTR). This is part of my work for my thesis in graduate school.

I have a fixed logic Block. And one reconfigurable Logic Block. Fixed Logic Block is a processing engine (PE). The data for that will be available in the Reconfigurable Logic (RL). I can either use the LUTs as distributed RAM or just use BlockRAM to store my data in the RL Block. My PE will work on the data and when it is finished I will read the output from the PE. And then, I will load the Reconfigurable block with the new data to be worked on by the PE. So all I have to do is change the contents of the LUT/BlockRAM using JBITS and partially reconfigure the Device for the new data to be worked on by the PE. And this is all the device does -- load the Data into the Reconfigurable Logic Block and let the PE(Fixed Logic Block) do the math on it, and this goes on. I am okay with the reconfiguration delay. Having said that, I believe the Performance/cost (Savings in terms of Area) would be improved this way rather than implementing everything in parallel (if this requires lets say a million PEs to be implemented) across an array of FPGAs. This ofcourse is not true if all I need is a few PEs.

My goal is to eventually make this a scalable appication with a Big Virtex Device with multiple PEs all working on the Data which will be reconfigured using RTR. And finally, develop a platform to have this done over a huge array of FPGAs

Does anyone know of any work done on this? I would appreciate your comments and suggestions.

1) Can a Virtex device handle this sort of Partial RTR ? Is there a thumb rule regarding how often partial RTR can be done and if this can be done for the life of the device? ( I apologize if this sounds ignorant, I just want to make sure before I spend more time and resources )

Thanks, Kode

"> Lets say I have an application that needs the following:

This can and has been done. Xilinx FPGAs use fully reprogrammable SRAM configuration cells with no wear-out mechanism.

Partial reconfiguration is a bit trickier but not rocket science either. Here are a few links that might prove useful.

Partial Reconfigurability Frequently Asked Questions

Virtex Series Configuration Architecture User Guide

Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. Spartan-3/II/IIE FPGAs

--------------------------------- Spartan-3: Make it Your ASIC

If you generate the ll file you can see the bit locations of the rams and lookup tables that you use. You can do Partial configurations all you want. The FPGA will last as long as a RAM.

Steve