FPGA Programming using Block Design Files or Graphic Design Files

Hi joe,

I use graphical only on top level,that to when I would like to alter the top level components and experiment with the components and their interfacing becausing it is easy for me to alter the connections.

If I knew the connections between the components and if am sure that those top level blocks/modules and their interface is fixed then I will code it in HDL.

I am also interested to know what others think of this approach.

thks & regds, Monica, Germany

Funny, I just had a similar conversation with coworkers this morning who asked why I didn't use a schematic for an FPGA design.

I never use anything other than VHDL sources in my designs. That's the only way you can guarantee portability between chip vendors, as well as saving your bacon when a vendor decides that he doesn't like the current schematic/block-diagram format/tool and changes it.

Plus, commenting in block diagrams and schematics is a pain.

Plus also too, I like to have real VHDL testbenches.

-a

I like a graphical view of a design but prefer text as the source.

With a good editor, copy/pasting of HDL instances and wiring them up is no more difficult that moving boxes and wires around graphically and typing in labels.

With an RTL viewer you can let the computer draw multi-level schematics for you from the HDL text files.

With an HDL simulator you can verify that all the wires are correct without even looking at the HDL or schematic views.

-- Mike Treseler

I just wanted to say that I write all of my code in text form, but I create a symbol of the text code. Then in my schematic page, I just insert the newly created symbol. I thought I needed to add this piece of information. When everything is done I have a nice functional diagram and when I click on the symbol it opens up my text code, written in .VHDL, or Verilog, or Altera's AHDL (which is very easy to write). I'm using Quartus and MaxPlus both from Altera. I don't know if you can do this in Xlinx or other FPGA IDE's. A great idea to help manage a complex design.

I'm so happy to hear people discussing this topic and appreciate all responses.

thanks, joe

snipped-for-privacy@hotmail.com wrote:

Andy,

I know that commenting in schematics is a pain, but if you give your schematic (FPGA project) to someone else they could gain so much information pertaining to the design and any assumptions/comments that needed to be passed on. Most people I work with say, "I do all my documenation in Power Point" and I say that doing it in the schematic it is already there and there's no need to start a Power Point project. Document as you go. Just my thoughts, do what works well for you and thanks for your comments.

joe

I guess whether you can use this block-diagram-linked-to-code method depends on how you partition and code your design. I don't see any gain in insight if you have a bunch of small blocks connected together, and each of the small blocks has, say, a mux or a register. I'd guess that you have a bunch of disjoint files called MUX16_1 and such, each containing a simple entity, and I agree that there's a lot of typing involved in wiring these things together.

I hate having to constrain my coding style to fit a tool that'll change with the next release.

-a

I just wanted to say that I write all of my code in text form, but

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in that field and also donot know that xilinx provides this featur or not.I am using xilinx spartan-2 and so working on ISE 7.1

things to make documentation for my final year project side by sid with project , and also it may things more clear

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