FPGA Programming solution

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Greetings , I am trying to implement a solution for an FPGA that needs
to be configured with two different programs because the whole system
will operate in two different modes. Basically what I need is a device
that contains two programs and depending on the user will program one
of each. The pinout will be the same because it is a digital filter.
One thing that came to my mind is putting a PIC that would emulate a
PROM and would retrieve the corresponding program from a FLASH
memory.

Do you know how can I optimize this?
Is there any commercial solution around?

Thanks in advance , and sorry for my bad english.

Alfredo

Re: FPGA Programming solution
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Alfredo,

Two solutions in my knowledge,

Try Dynamic Partial reconfiguration, If you are using Xilinx FPGA's,
try MicroBlaze as configuration controller. It may require a bit of
effort from your side.

Use a Micro-controller as configuration controller, configuring the
FPGA in Slave serial mode through Micro-Controller is far easier than
emulating the functionality of PROM through Micro-controller.

Hope this helps
/MH

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If the functions of the two programs are so similar, is it possible to
contain them in a single configuration?

For configuration with an external microcontroller, it's probably best
to use "passive configuration" mode.

How fast do you need the configuration to load?  It can take a long
time when done with an external micro!!

For example, I use hand-optimised PIC assembler to load a compressed
configuration to the smallest Altera Cyclone II.  The PIC is clocked
at 32MHz and controls only the clock signals.  (The data is connected
directly from the flash memory (an SD card) to the FPGA configuration
data input).

Even in this "Formula 1" arrangement (with loop unrolling and with the
SD card and FPGA configuration clock signals on the same PIC port to
save one instruction of the loop), it takes about 0.3s to load the
FPGA.

Mike

Re: FPGA Programming solution
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Hi again , the function is similar but the design is different. I
mean , both are digital filters but they use different architectures.

1- Where can I read about Dynamic Partial ? I am not using a very
large FPGA ( xc3s500e) so I dont know if a Microblaze processor would
fit in.
2- I will study a bit more about Slave serial mode but I dont
understand how this can help me choose which program I will load on
the FPGA.
3- Programming time is not an issue since it will be programmed once
or twice a month in the worst case.
4- Has anyone evaluate SystemBIST , is it expensive ? not really
useful? unconvenient?

Thanks again , and sorry for my bad english.

Re: FPGA Programming solution
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I understand from
http://www.xilinx.com/support/documentation/application_notes/xapp502.pdf
that Xilinx "slave serial" mode is equivalent to Altera "passive
serial mode".

In this mode, the microcontroller loads the FPGA, so you have complete
control in the microcontroller program of what data is sent to the
FPGA as its configuration.

Mike

Re: FPGA Programming solution
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fromhttp://www.xilinx.com/support/documentation/application_notes/xapp502 ...
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I think I will focus on Multi-Boot PROM , any experience with that?

Re: FPGA Programming solution
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No.

Re: FPGA Programming solution
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With Xilinx FPGAs, the fastest solution with a micro is usually one of
the SPI modes. And a fast micro, of course. A little PAL or another FPGA
will be at least as fast. Maybe this is also true for Altera.

Re: FPGA Programming solution
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Let's race your SPI solution against my hand-optimised assembler!!  :)

I have to warn you that my method transfers at a peak rate of one
configuration bit every 375ns (three instruction cycles) and an
average of about one bit every 420ns over each 512-byte block from the
flash device.  (There's a delay in requesting each block which would
apply to any method).

If you use SPI, you'll first need to read the flash data into your
processor.  With byte-wide flash, you have an advantage there and may
overtake me (although you'll use a lot more processor lines).  With
serial flash, it will take longer to read the data to your processor
(unless you use another SPI controller for that) than it takes me to
send it on the direct connection between my flash memory and the FPGA
by just toggling the clocks.

With parallel flash memory, you could still use direct connection.
This would waste all but one bit in each flash word, but that may not
be significant if the flash memory is much larger than the FPGA
configuration.

Mike

Re: FPGA Programming solution
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Ok , so here we are. We are evaluating between using a 16Mb PROM that
you can use for Multi-boot ( USD $16) or doing it with a processor
that would read all the programs from different Flash memories. In
case we use the last one , I will evaluate wether use SPI or hand-
optimised Assembler code.

What do you think of that?


Re: FPGA Programming solution
The Xilinx Platform Flash with Revisioning is a great, simple way to
do this.  With a parallel interface, it's very fast, and it comes with
JTAG in-system capability.

A lower cost alternative is Master SPI MultiBoot, which is available
on the Spartan-3A series of FPGAs.  Spartan-3E supports MultiBoot
through parallel flash or Platform Flash.  Spartan-3A can also do it
with SPI flash and can support as many images as your flash will
hold.  See the Master SPI Mode and Reconfiguration and MultiBoot
chapters in UG332
http://www.xilinx.com/support/documentation/user_guides/ug332.pdf

One restriction with SPI is that the first configuration always takes
place at address 0.  So, you may have to have a "Selector" bitstream
that takes user input to decide whether to redirect to Application A
or Application B.

You can see a simple example of this for the Spartan-3A Starter Kit on
the Avnet Design Resource Center (sorry for the long URL)
https://www.em.avnet.com/common/filetree/0,2740,RID%253D0%2526CID%253D44394%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526PVW%253D%2526PNT%253D%2526BID%253DDF2%2526CTP%253DSTA,00.html

Bryan

Alfreeeeed wrote:
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Re: FPGA Programming solution


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I have a scheme that I have worked out to use the SST25VF010-20-4C-SAE
chip, $0.98 in 100 piece quantity, that's a 1 MBit serial flash.  They
have several larger versions, like the 8 MBit one is ~$3.00 !
I use a pair of LVQ CMOS logic chips to send the correct instruction
to the chip to prepare it to read from the beginning.  It would require
adding one additional chip to extend the number of programmable bits so
you could select the starting location within the PROM to select the
desired program.  This requires no CPU whatsoever, and the 2 or 3 logic
chips are tiny SSOP parts costing no more than $0.25 each.  The SPROM
can keep up with the Xilinx master-mode configuration clock, so you
don't need to provide a special clock for it.

Jon


Re: FPGA Programming solution
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how about wiring the prom clock to a pin that can be used as a timer
output, at startup you
can use the pin as io and bitbang the prom the usual way to pick the
right starting address
and give it the right read commands, after that enable the pin as a
timer output and run as
fast as the timer will go...

-Lasse

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Maybe that would work in some cases.  The number of clocks would need
to be well-defined (to match exactly the size of a data block).  The
micro would then need to discard the CRC which follows the data.  (It
needn't check it as the FPGA will check the CRC on the whole of the
configuration).

In my case, the clock to the flash memory must be set before the clock
to the FPGA (although they can be cleared at the same time), so a
single signal won't work.

Mike

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oh, I didn't notice you used an SD card, I was imagining a regular
serial prom where you can just keep on clocking till you have enough
bits.

-Lasse

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Of course, an SD card wouldn't be first choice for storing the
configuration, but the application is based on SD card, so it makes
sense to fetch the configuration from there, too.

Mike

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Looks like SPI Master Mode is the option. I am interested in Jon's
alternative of putting a memory twice the size a program need. Any
ideas how to implement this? BTW , I also need to program two FPGA
with the same program so I would need to do daisy chain with a
Spartan-3E.

So for my bad english and thanks

Alfred

Re: FPGA Programming solution


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Well, I'm not going to reveal all my secrets for free, but a fairly
simple scheme can be figured out for the SST chips.  They need an
"instruction" byte serially shifted in to program the memory to read
from the beginning.  The Xilinx FPGAs all seem to ignore everything
before a byte of "FF" which appears right after a short header in the
BIT or MCS file.  Wiring up a 4-bit counter and a gate chip was the
minimum package count scheme I could come up with for that bare minimum.
If I needed to program a few bits of the starting address, too, that
would probably expand to a 3-chip solution.  These SSOP-packaged parts
are pretty small.

I also built my own programmer for the SST chips, as none of the device
programmers would handle them.  It was a one-evening job to get the
programmer working.  One bit from CPU to PROM, one clock bit, one
data bit back from the PROM.  Pretty simple, plugs into the parallel
port.  I wrote it in C for Linux, just my personal choice.  The way I am
setting it up doesn't allow for on-board programming, I DON'T want to
give my customers that option.  But, there's no reason that couldn't be
provided
easily.

Jon


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I've often wondered why these Serial FLASH vendors have missed the
REALLY OBVIOUS option, of alias of a 00 or FF opcode to read,
so you could simply connect their serial memory, and just clock to
stream out data. Would be 100% upward compatible with present
usage.

-jg


Re: FPGA Programming solution
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45LF010 had a 0xFF read opcode, but its eol ...

-Lasse

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