FPGA/PLD Reliability: High Speeds and Advanced Processes

Hi,

I am interested in the reliability of modern FPGA/PLD hardware and am surveying groups of users for their experience along with studying reliability data provided by various manufacturers. So, two basic questions:

  1. Are there reliability issues for modern devices with the higher clock speeds that we are using today? I shall set, for the sake of discussion, an artificial boundary of 100 MHz clock frequency for the dividing line between high and not high speed.
  2. Are there handling/assembly/application issues for modern devices as compared to say devices from 5 years ago? That is, are there observed changes in sensitivity to conditions such as ESD, input voltage excursions, transients on the power supplies, etc.

Please categorize the application environment in terms of commercial, industrial, or mil/aerospace and specify clock frequency. If possible, quantities of devices might be helpful for evaluating trends.

Posts to the newsgroup are of course fine. If you wish to be anonymous, please demunge and use the e-mail address in the header.

Thanks,

Richard B. Katz NASA

Reply to
Richard B. Katz
Loading thread data ...

You also might like to consider packaging. The high performance we achieve today owes as much to the packaging as to the silicon. New packaging (e.g. BGA) will have new ways to fail.

High performance also means lots of power, and the thermal aspects may influence reliability.

Regards, Allan.

Reply to
Allan Herriman

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.