Hi,
I am interested in the reliability of modern FPGA/PLD hardware and am surveying groups of users for their experience along with studying reliability data provided by various manufacturers. So, two basic questions:
- Are there reliability issues for modern devices with the higher clock speeds that we are using today? I shall set, for the sake of discussion, an artificial boundary of 100 MHz clock frequency for the dividing line between high and not high speed.
- Are there handling/assembly/application issues for modern devices as compared to say devices from 5 years ago? That is, are there observed changes in sensitivity to conditions such as ESD, input voltage excursions, transients on the power supplies, etc.
Please categorize the application environment in terms of commercial, industrial, or mil/aerospace and specify clock frequency. If possible, quantities of devices might be helpful for evaluating trends.
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Thanks,
Richard B. Katz NASA