FPGA pin swapping utility

Mentor's "IO Designer" does just that. You use it to create schematic symbols that can be changed dynamically. So you can finish the schematic and change just the symbols later when optimizing the pin out.

You can import your PCB-Layout (after all components are placed) and use IO-Designer to "unravel" busses and optimize the pinout.

It also knows about bank supply voltage rules, clock pins/regions and so on (so it won't let you put an LVCMOS18-output in a bank that already has a LVTTL-Output or let you put a clock on a regular IO), which can be a big help.

It can also generate a conatraint file for your FPGA (UCF or SDC) and a top level HDL-file.

But as all Mentor products it's quite expensive and has its quirks...

HTH, Sean

In my experience, setting up the automated tool has taken longer than "just doing it".

My design flow is OrCAD->(Q2/ISE)->PADS. I go into ECO mode in Pads, and clean up the routes, part data sheet in hand. I take the "was-is" file from PADS, and translate it into a pin-swap file for OrCAD, and then update the pinout (constraint) file for the FPGA.. After a couple of boards, I've learned how to "see" the routes (ie BGA->QFP) when pinning the FPGA, so it typically takes only two passes to get it right.

Truth is, I would have trouble trusting a low-end tool to get it right; I've seen the Mentor tool make mistakes (mostly from pinswap parameters being entered wrong, but a mistake is a mistake.)

G.

For Cadence Allegro Design Entry (aka ConceptHDL), we use a "bit- sliced" symbol where each IO pin has a common Vcco pin. You can hard- assign pin numbers you need, and let Allegro (board layout) auto or manually swap the remaining pins. Having the common Vcco pins keeps Allegro from swapping IO pins that have their Vcco pin tied to a different voltage (or just signal name). The advantage of this approach is if you have multiple banks powered from one voltage, you can swap freely between IO pins in any of those banks. You can lock IO pins into specific banks by temporarily assigning a unique signal name to that bank's Vcco pins. Then when you're done swapping, tie all the appropriate banks' Vcco pins to the correct voltage signal.

This works very well as far as it goes, but it does not allow you to constrain smaller groups of pins (say around local clocks, etc.), but still allow swappability within those smaller groups.

Andy

You can also use scripts in PADS to (relatively easily) scan the FPGA and export a revised Pinout to the FPGA tools. You then confirm that is routable in the FPGA/CPLD tool flow. Only design constraint is you need to match the NET names to the fpGA signal names, but who doesn't do that ? :)

-jg

Xilinx Planahead does just that. I have successfully used this for a V5LX50-FF1153 design. This has several features apart from pin planning (PinAhead), including easy definition of placement constraints for meeting timing etc. Handy for pin planning is the ability to output a CSV file of the pins and I/O standards, which could then easily be imported into your PCB program (without scripting etc.). You can also reimport the CSV file and it will update the UCF.

This is downloadable from the Xilinx website. According to Avnet Silica this software is being made free, even though it doesn't appear like that from the Xilinx site. The only irritation is that you have to download a new eval licence each month (have done this for the last 5 months).

Andrew