Hey all,
I have some questions on ISE/EDK. I would really appreciate some help.
Before I start, some explanation of my project. It's called Network Encryption Engine. There are two components in the project, Client and Server. Client is our FPGA board. Whenever client has request use a specific encryption standard (we just using AES only). It will connect to server and download the bit-stream and run it on FPGA and will give the necessary outputs.
Question A For simple case, we assume the AES part is available locally. Our code for AES is on Verilog. Our application is running on PowerPC developed by EDK. Problem is right now interfacing these two.
For simpler case, like full adder in Verilog and Simple C application to write the UART (HyperTerminal), how do I integrate it so that I can read the input (full adder) from UART and write it to ports on the Verilog code and display the output back in the UART.
Question B For network development part, there are several options a. XIlnet b. RTOS like Vxworks, Linux c. ucLinux d. Connect to another board which has TCP/IP Stack already enabled.
-Found the Xilinx site that, option (a) is not stable and unreliable
-BSP for option (b) came with the ML310 board, but IDE's to develop application need to be bought and are expensive.
- ucLinux must be ported to ML310 Microblaze design
- d is most viable option now.
Is there any other options we can use to develop this.?
Technical Details Development Board: ML310 FPGA: Virtex 2 Pro
Thank you in Advance
Cheers Shakith