1. Home
  2. Field-Programmable Gate Arrays
  3. FPGA: Model-SIm XE problem

FPGA: Model-SIm XE problem

Hi I have made a generic component like below

entity fifo is generic( AW : integer; PROG_EMPTY_THD : std_logic_vector(AW downto 0); PROG_FULL_THD : std_logic_vector(AW downto 0) ); port ( rst : in std_logic; write_address : out std_logic_vector(AW-1 downto 0); read_address : out std_logic_vector(AW-1 downto 0); wr_clk : in std_logic; ..... );

This component fifo is instantiated in my design with different values for AW.

My design is synthesizable and it is actually working in hardware too.

But with Model-sim XE simulator it gives the following error < Object 'aw' cannot be used within the same interface as it is declared.

This error is pointed to my component declared package.

is there any work around for this problem.

any pointers will be helpful.

rgds bijoy

When model-sim compoiles the fifo module separately, it sees AW constant and it is used in std_logic_vector(AW downto 0)

so i think it is not able to determine the width of the vector ..

Reply to
bijoy
Loading thread data ...

hi bijoy ,

you could declare AW or even different AW (AW1, AW2, AW3 ...) in a separate package (which could also be used for synthesis of course) By doing so Modelsim should have no problems to identify the length of the std_logic vector in the corresponding instantiation.

Rgds Andr=E9

Reply to
ALuPin

The problem is that you are using AW within the generic declaration area. The way you are doing that is a bit unusual too. Make PROG_EMPTY_THD a signal instead of a generic, and the problem should go away.

Reply to
Duane Clark

Oops, and of course also PROG_FULL_THD.

Reply to
Duane Clark

You could pass the generics as natural and do the vector conversions elsewhere as shown below.

-- Mike Treseler

--____________________________ library ieee; use ieee.STD_LOGIC_1164.all; use ieee.numeric_std.all;

entity fifo is generic(AW : natural := 16; PROG_EMPTY_THD : natural := 255; PROG_FULL_THD : natural := 22222); port (rst : in std_logic; write_address : out unsigned(AW-1 downto 0); read_address : out unsigned(AW-1 downto 0); wr_clk : in std_logic); end entity fifo;

architecture synth of fifo is subtype vec is unsigned (aw downto 0); constant empty_c : vec := to_unsigned(PROG_EMPTY_THD, AW); constant full_c : vec := to_unsigned(PROG_FULL_THD, AW); begin -- architecture synth end architecture synth;

-- vcom -93 -quiet -work work /evtfs/home/tres/vhdl/play/fifo.vhd

-- Compilation finished at Mon Feb 27 11:12:45

Reply to
Mike Treseler

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.