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FPGA + Mess o' RAM

Does anyone have any experience connecting an FPGA to a serious mess of DRAM? I'm thinking of something on the order of 16GB, possibly just by buying/socketing 4x4GB standard DIMMs.

I don't need tremendous throughput; if I could average 50 MB/s I'd be fine. For sheer density I'm thinking DDR2. I'd like to avoid DDR3 if I can, simply because of the lack of support on low-end FPGAs. I could certainly go slower, say DDR1 or even SDR, but that seems to imply buying chips by the bucketload per board, and my assembly people will shoot me.

Ideally this would be a Cyclone 3/4 project. Maybe Spartan 6 instead. The actual signal processing requirements are low, so I don't need that much crunching horsepower.

Anyone manage to do something like this?

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Rob Gaddi, Highland Technology -- www.highlandtechnology.com
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Reply to
Rob Gaddi
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I don't recommend Spartan 6 for this application. Its internal memory controllers only handle single chips - not DIMMs. So even with a large S6 and multiple MCB's you can't get up to

16GB. And S6 is sufficiently slow without the MCB to make DDR2 a nightmare.

If you want to run really slow, you might want to look into LPDDR memory, which can run with a much lower clock speed making the extra net lengths, loads, etc. more manageable.

-- Gabor

Reply to
Gabor

Many years ago I've created a design which used a standard DDR module at 100MHz on a Spartan2 (lowest speed grade). Actually the memory was shared between 2 FPGAs due to lack of pins. I did roll my own DDR controller because the MIG tool produced an overcomplicated interface and didn't even allow for 32 data lines. Most FPGA vendor solutions aim at achieving the highest memory bandwidth. Usually at the costs of enormous amounts of logic. At lower speeds things get much easier.

IIRC DDR2 has a lower speed limit of 133MHz which shouldn't be a problem. I think my old design would also be able to use DDR2 if I used a higher speed grade FPGA. I used a 90 degrees shifted clock to capture the data read from the memory. It took some arm wrestling with the tools to get worst case setup and hold timings which I needed to calculate/determine if there was a window in which the data was valid. This is much easier than trying to use the DQS signal as a clock for a FIFO. More logic adds more timing uncertainty when dealing with external signals.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
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Reply to
Nico Coesel

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I don't believe that you will find low end FPGA that officially supports such amount of RAM. May be, mid range, like Arria GZ, but even then, it seems to support ether 1 DDR3 DIMM per channel or 2 DDR2 DIMMs, so hitting 16 GB wouldn't be easy.

On the other hand you can relatively easily connect 2x8GB DDR3 DIMMs to smallest Stratix3 or Stratix4.

There is another interesting option - do it backward! I mean, build PCIe board around Cyclone-4 GX and let host PC to serve as your memory controller. Plugging 24 GB into PC nowadays is cheap, easy and reliable. The latency over PCIe will be ~5 times higher than via direct connection, but you will get plenty of bandwidth, something around 150 MB/s for x1 gen1 link.

Reply to
Michael S

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