Types are good. But why do I have to write 'signal x : std_logic_vector(31 downto 0)' when I could just type 'logic [31:0] x' ?
I agree completely. But you can be explicit without hurting your keyboard. Spend the keystrokes where it matters.
(I'm fed up of reading through pages and pages of Verilog code that merely describes the interfaces to a component, which does a tiny amount of work and then instantiates another component that's almost the same inside it. When you get 8 levels down in this tree of input and output wires it gets very tiresome)
So why is there a standard if tools can cherry pick what is and isn't supported? One of my colleagues has a table of what SystemVerilog features are supported across different tools. To have a multi-tool project, you end up with the lowest common denominator, at which point most of the useful features aren't an option.
BSV has its own simulator, which simulates at a higher level of abstraction so runs a lot faster than a Verilog simulator. You can, of course, simulate the verilog if you want to, but generally we find that code that simulates in the BSV simulator will work first time on FPGA.
(The tricky bit is dealing with external IP like DRAMs - to get better testing coverage we have randomised models in BSV, rather than simulating the DRAM controller and DRAM IP in Modelsim)
function Bool i2xj( td i, td j ) provisos( Arith#(td), Eq#(td) ); return ( (i - 2*j) == 0 ); endfunction
is a polymorphic combinatorial function that takes two inputs i and j. We don't know the type of i and j, but we do know that it must be the same, the type (we'll call it 'td') must support arithmetic and testing equality. If it doesn't, it's a compile error. So I couldn't use this for a string, for example.
For any instantiation of this function, we'll accept the parameters i and j and generate logic that computes i-2j and compares it to zero, returning a boolean value.
If I wanted to instantiate this in a module, I'd do something like:
// define some registers with their types and default values Reg#(UInt#(64)) f