Hi
FPGA : Spartan-3, Xilinx ISE :tools ------------------------------------ have wrote a VHDL code to implement shift registers
as shown below
type reg_array is array(7 downto 0) of std_logic_vector(7 downto 0);
signal reg : reg_array;
process(clk) begin if(clk'event and clk = '1')then if(en = '1')then reg