FPGA : MAP slice logic into BLOCK RAM

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Hi

FPGA : Spartan-3, Xilinx ISE :tools ------------------------------------ have
wrote a VHDL code to implement shift registers

as shown below

type reg_array is array(7 downto 0) of std_logic_vector(7 downto 0);

signal reg : reg_array;

process(clk) begin if(clk'event and clk = '1')then if(en = '1')then reg <=
reg(14 dwonto 0) & din; end if; end if; end process

want to map this logic to BLOCK RAM instead of slices.

have done this by enablling the option in MAP properties of ISE.

But what i observed is it uses BLOCK RAM but occupies slices also.

Can anyone help me in this regard

whether i am doing anything wrong ?

regards bijoy

Re: FPGA : MAP slice logic into BLOCK RAM

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the logic is that ISE can auto map to BRAM is ver limited and specific, read
the datasheet and manuals it is explained there what type of logic can be
auto mapped to BRAM

antti



Re: FPGA : MAP slice logic into BLOCK RAM
Hi

I have read that, it says we should not use asynchronous reset

The program what i have written is also taken from there and they say it will be
mapped to BRAMs

I am observing in my p&r report that it is getting mapped to BRAM but the slice
count is not getting reduced.

regds bijoy

Re: FPGA : MAP slice logic into BLOCK RAM
First off, I think it's better to instantiate BRAM than inferring it.
When you go to the restaurant
and you want veal, you should say it, don't describe the veal to the
waiter :)
The other issue is that your FFs are read from and written to in the
same clock. I vaguely
remember reading and writing to the same BRAM address is a bad idea.

bijoy wrote:
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be mapped to BRAMs
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slice count is not getting reduced.
Quoted text here. Click to load it


Re: FPGA : MAP slice logic into BLOCK RAM
Hi I don't know how to implement a shift register using BRAMs. That is why i
tried to use the map property to enable the mapping option.

If any one has an idea, could you please share it with me.

regards bijoy

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