FPGA : MAC FIR doubt--HELP ME PLEASE

If previousaly, you were using one BRAM to run both the FIR, then you have to use two different dual port BRAM for dynamic coefficients, one for each FIR filter engine.

Use one port for writing co-efficents and the other port for reading. Configure your BRAM to 'read before write' to avoid reading new coefficients in case of address conflicts.

Cheers, Sunil

As far as I can see (and I may be wrong), you cannot easily do this since the core does not expose any control/update signals to halt the filtering operation and take new coefficients a la the distributed arithmetic core.

It may be possible to disable the filter, and then update the coefficients in the pertinent BRAM, then reset the filter and ignore the transient output samples from the previous coefficient config but I have never done this?

Anyone that has?

One of the troubles with the Coregen cores is that you can't get to the internal nodes in the design. That means for a filter that uses the BRAM, you can't get to the other port to reload the coefficients. You have two options: you can write your own filter (it isn't that hard to do, just a little time consuming), or you might be able to use the adaptive filter core instead: I think that leaves an external mechanism for updating the coefficients.

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Hi Ray Andraka

Thank you for your reply.

Now I was writing my own FIR with Multipler and adder units....I could complete it in a day, but i just wrote plain VHDL using some arrays to store the filter state. so it takes lots of slices. Now i am trying to put in dual port ram.

am trying to fit the design in my FPGA spartan-3 (50K device the lowest available) of which i am already using 68 % of the slices.. I have already 2 FIR filter running in my FPGA, this is the 3rd Filter which need to be adaptive one.

But you were telling about adaptive filter core , but it is not available in my coregen. i am using ISE 6.3. in which version of ISE adaptive filter is available.

Thanks a lot for your reply... regards bijoy

Hi

I have made a FIR filter using multipler components and BRAMs

But i am facing problems during timing simulation, it works fine during functional simulation.

will explain little bit about other components involved in my design

In my design i have a 35.328 MHz base clock

have multipled it by 2 and used to run another FIR filter (32 tap decimation available from core gen) this is a fixed tap one

Now i multipled 70.656 MHz output of my first DCM again by 2 to get 140.312 MHz which is given to the new 32 tap FIR filter i made as described above (ie using descrite components , multipler,BRAM etc)

I need to run it at 140.312 Mhz as my input data rate is at 4.416 and the number of tap filters are 32. (i can split it into two 16 tap filter but in that case i need 4 BRAMs for this filter itself, in that case i cannot accomodate other filters which is already existing in my design, as i am currently using xc3s50 device which has got 4 BRAMs only)

functionally it simulated well

but during timing simulation i am getting this error in my model sim simulator

===================================

Time: 9898215 ps Iteration: 3 Instance: /tb_gl/uut/glrx_1_tde_filter_comp_tde_filter1_multiply_comp_bu138 # ** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.381 ns; Observed := 0.055 ns; At : 9898.226 ns # Time: 9898226 ps Iteration: 3 Instance: /tb_gl/uut/glrx_1_tde_filter_comp_tde_filter1_multiply_comp_bu142 # ** Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.381 ns; Observed := 0.328 ns; At : 9898.5 ns # Time: 9898500 ps Iteration: 3 Instance: /tb_gl/uut/glrx_1_tde_filter_comp_tde_filter1_multiply_comp_bu152 # ** Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK;

==================================

what is this error means. i think there is some set-up violation but how do i debugg this problem

how can i see the internal signals during timing simulation ?

please advice me in this regard

thanks

bijoy

"bijoy" schrieb im Newsbeitrag news: snipped-for-privacy@webx.sUNCHnE...

decimation available from core gen) this is a fixed tap one

140.312 MHz which is given to the new 32 tap FIR filter i made as described above (ie using descrite components , multipler,BRAM etc)

You better use just one DCM and use CLK2X and CLKFX (with M set to 4). This way your clocks are well phase aligned. This can also work with two DCMs, but more things can get messed up (And I guess two cascaded DCMs generate more jitter than just one, right?).

simulator

/tb_gl/uut/glrx_1_tde_filter_comp_tde_filter1_multiply_comp_bu138 # ** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK; # Expected :=

0.381 ns; Observed := 0.055 ns; At : 9898.226 ns # Time: 9898226 ps Iteration: 3 Instance: /tb_gl/uut/glrx_1_tde_filter_comp_tde_filter1_multiply_comp_bu142 # ** Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.381 ns; Observed := 0.328 ns; At : 9898.5 ns # Time: 9898500 ps Iteration: 3 Instance: /tb_gl/uut/glrx_1_tde_filter_comp_tde_filter1_multiply_comp_bu152 # ** Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK;

do i debugg this problem

It says something about a HOLD violation, not a setup violation. Make sure your input signals change NOT exactly in the same moment as your clock. Delay the input signals by lets say 3ns after the active (rising ?) clock edge.

You have to add them to the wave window (Befor you start simulation, otherwise no data is recorded for these signals)?

Regards Falk

Hi But for timing simulation if i add the signals of my internal modules, i am not able to make out the signals i used in the design and the signals it shows in the wave window

don't know how to interpret the signals shown in the wave window to signals i defined in my design

regards bijoy