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FPGA Interconnect

Hi,

Here is a question little bit in the internals of the FPGA. I am asking this more out of my curiosity and learning.

FPGA LUT typically consists of SRAMs & a Mux at the output. These Muxes need both normal & inverted select signals. The select signals come from the interconnect. Considering the inverted select signals, there are two possible implementations ?

Implementation-1 CLB-1 [To] Switch Mux [To] Switch Buffer [To] Interconnect Line to Carry TRUE Signal [To] CLB-N

In such a case there have to be inverters within the LUT Mux to get inverted signals.

Implementation-2 CLB-1 [To] Switch Mux [To] Switch Buffer [To] Interconnect Line to Carry Normal Signal & Interconnect Line to carry Inverted Signal [To] CLB-N

Implementation-2 will be inefficient in terms of area & power. However Implementation-1 will have additional one inverter delay in the critical path.

Does anybody has an idea which one is favored in the FPGAs. Please get back.

Thanks, Bukka

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Reply to
bukka
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At the risk of misunderstanding your question, I think that your "Implement= ation-1" would not really have an additional inverter delay if it's going t= o be input to a function that will fit into a single LUT (up to 4 inputs - =

6 if you count the neighboring LUT in the same slice). The propagation del= ay through:

Y =3D A + B

is exactly the same as the delay through:

Y =3D (!(A * B) + C) * (!D + A)

because either is implemented as a 16-bit ROM with a 4-bit address input an= d a 1-bit data output.

So sending your inverted signal along with the normal signal would waste a = routing resource and the automatic tools would be unlikely to do it that wa= y.

Best wishes,

-- Kevin Smith HDL Nerd for Hire

Reply to
hdlnerd

Am Donnerstag, 7. Juni 2012 16:56:59 UTC+2 schrieb bukka:

Hi Bukka, I think it doesn't make much sense to think about the internals of a LUT in= terms of gates and wires. These blocks are highly optimized monolithic units made out of transistors. If any selection signals (which are the LUTS inputs) need inversion interna= lly, this functionality will be absorbed and timing optimized within the tr= ansistor layout the LUT is made of.

Have a nice synthesis Eilert

Reply to
goouse99

(snip)

That is true, but many engineers like to know how things work inside. In this case, your best hope is probably patents.

As it isn't so hard to open up an IC and figure out how it works, the best protection is a patent. Maybe not all the details you want, but some might be there.

-- glen

Reply to
glen herrmannsfeldt

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