Greetings,
I am new to hardware design and hoping to get a reality check on building a lexical analyzer and parser using FPGAs. I can see the following options.
- A hardwired implementation of some or all of lexer&parser to maximize the performance.
- Build a CPU with instructions optimized for interpreting parse tables and drive it with the output of a parser generator similar to YACC.
- Have a RISC-like CPU implemented on the FPGA executing a parser.
I see no advantage to option 3 over doing the same thing on a general purpose CPU. I don't know if the second option has any potential for increased performance. As far as the first option, I am wondering if the FPGAs currently available have the capacity to implement the hardwired parser for a language of low to moderate complexity and how hard it might be model it using a language like VHDL.
Please post any thoughts/comments/pointers about the various options.
Thanks