Allan Herriman schrieb:
Hi Allan, yes, I used some extreme examples to show what's possible with stuff that is widely available (especially to students) like Spartan2/virtex. There you rarely get system clocks above 100MHz for larger designs.
For the number of rounds I said "at least". That is 10 for the 128 bit key, 12(?) for the 192 bit key and 14 for the 256 bit key. Of course I chose the fastest option to get a higher result in the end.
Adding 4 clocks for the feedback mux might have been a little overestimated when using a single mode. But in the end it was just an example. No need to make a fuss about some 100 Mbits :-)
The 500 MHz,as mentioned, are just taken from the comercials. But I'm pretty sure it will be reachable with the Virtex 7 silicon (whenever that will be).
Well, unrolling the loops was what I meant with "additional rounds and decrease the number of iterations". Sorry if I didn't said it right.
For the Sonet encryptors you mentioned I found no information about the modes they use. Can it be possible that they use CTR-Mode? That one can use parallel engines indeed. All you need are modulo counters for each engine and feed them with incremental starting values. Also, for most modes including CTR you only need encryption rounds. I'm not sure if that helps any in sharing hardware, but at least you are working with only one kind of modules (e.g. only Sboxes and no invSboxes etc.) That eases the design of the chip a lot.
Best regards Eilert