FPGA functional flow..please help!

Hallo,

I am new in the world of FPGA. I am asked to design he functional flow for a image processing hardware. The hardware i.e FPGA will be used for video decompression . Hence it has to receive the video from the microcontroller and then execute a decompression algorithm . Now I am confused as to how the data (image/ video) will be managed by the FPGA before the decompression algorithm is executed. What are the blocks required in the functional flow . I am assuming there should be some functions required for buffering of data (for data in and out).

Can anyone please guide me on how I should go about designing the functional flow?

Regards.

Reply to
vibha
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I presume functional flow means block diagram.

I recommend a systolic array for image processing in FPGA. The buffering should be done on the microcontroller. (Which could be separate, or a soft processor in the FPGA.) It will then send data into the systolic array, and extract results some clock cycles later. The functional flow/block diagram will be the successive stages of the decompression algorithm.

-- glen

Reply to
glen herrmannsfeldt

Hi, you should have a look at some application notes first. (e.g those available from Xilinx) They even have reference designs that might be useful as a starting point.

But what is your real intent? Image processing or video decompression? Or both? Depending on the answer the best approach for your design will be different.

To learn about the functional flow, you might read the standards or specifications of the required algorithms. Then you need to develop a hardware oriented approach to implement these functions. It will be different from the straightforward mathematic formulas or programming examples because hardware design is based on a different paradigm.

Have a nice synthesis Eilert

Reply to
backhus

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