Hallo,
I am new in the world of FPGA. I am asked to design he functional flow for a image processing hardware. The hardware i.e FPGA will be used for video decompression . Hence it has to receive the video from the microcontroller and then execute a decompression algorithm . Now I am confused as to how the data (image/ video) will be managed by the FPGA before the decompression algorithm is executed. What are the blocks required in the functional flow . I am assuming there should be some functions required for buffering of data (for data in and out).
Can anyone please guide me on how I should go about designing the functional flow?
Regards.