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FPGA for a DVB common interface implementation

Hi,

anybody has any (practical) information about the Common Interface specification for DVB receivers?

I have some ideas (for example a DVB-CI module that feed the transport stream from DVB receiver to Ethernet) in order to analyse or broadcast to other devices in the network

I have the simplest implementation would be an FPGA with an embedded CPU.

Anybody knows about the Common Interface physical specification (pins,etc..) ? Any reference design or anything that can help in kick off the idea?

I have seen "oficial" documentation from ETSI, CENELEC, etc. but it is too general to start quickly

Thanks, Manuel

Reply to
manuel-lozano
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Hi,

anybody has any (practical) information about the Common Interface specification for DVB receivers?

I have some ideas (for example a DVB-CI module that feed the transport stream from DVB receiver to Ethernet) in order to analyse or broadcast to other devices in the network

I have the simplest implementation would be an FPGA with an embedded CPU.

Anybody knows about the Common Interface physical specification (pins,etc..) ? Any reference design or anything that can help in kick off the idea?

I have seen "oficial" documentation from ETSI, CENELEC, etc. but it is too general to start quickly

Thanks, Manuel

Reply to
manuel-lozano

The CI interface is a synchronous interface with frame & byte sync and 8-bit data. I think it's daisy chained too. It's not that complicated I think. Just search on google a bit to find.

Reply to
sky465nm

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